125 lines
4.8 KiB
C
125 lines
4.8 KiB
C
/* $NetBSD: am79c930reg.h,v 1.2 1999/11/05 05:13:36 sommerfeld Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Bill Sommerfeld
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Device register definitions gleaned from from the AMD "Am79C930
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* PCnet(tm)-Mobile Single Chip Wireless LAN Media Access Controller"
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* data sheet, AMD Pub #20183, Rev B, amendment/0, issue date August 1997.
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*
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* As of 1999/10/23, this was available from AMD's web site in PDF
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* form.
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*/
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/*
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* The 79c930 contains a bus interface unit, a media access
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* controller, and a tranceiver attachment interface.
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* The MAC contains an 80188 CPU core.
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* typical devices built around this chip typically add 32k or 64k of
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* memory for buffers.
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*
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* The 80188 runs firmware which handles most of the 802.11 gorp, and
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* communicates with the host using shared data structures in this
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* memory; the specifics of the shared memory layout are not covered
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* in this source file; see <dev/ic/am80211fw.h> for details of that layer.
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*/
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/*
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* Device Registers
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*/
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#define AM79C930_IO_BASE 0
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#define AM79C930_IO_SIZE 16
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#define AM79C930_IO_SIZE_BIG 40
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#define AM79C930_GCR 0 /* General Config Register */
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#define AM79C930_GCR_SWRESET 0x80 /* software reset */
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#define AM79C930_GCR_CORESET 0x40 /* core reset */
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#define AM79C930_GCR_DISPWDN 0x20 /* disable powerdown */
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#define AM79C930_GCR_ECWAIT 0x10 /* embedded controller wait */
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#define AM79C930_GCR_ECINT 0x08 /* interrupt from embedded ctrlr */
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#define AM79C930_GCR_INT2EC 0x04 /* interrupt to embedded ctrlr */
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#define AM79C930_GCR_ENECINT 0x02 /* enable interrupts from e.c. */
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#define AM79C930_GCR_DAM 0x01 /* direct access mode (read only) */
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#define AM79C930_GCR_BITS "\020\1DAM\2ENECINT\3INT2EC\4ECINT\5ECWAIT\6DISPWDN\7CORESET\010SWRESET"
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#define AM79C930_BSS 1 /* Bank Switching Select register */
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#define AM79C930_BSS_ECATR 0x80 /* E.C. ALE test read */
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#define AM79C930_BSS_FS 0x20 /* Flash Select */
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#define AM79C930_BSS_MBS 0x18 /* Memory Bank Select */
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#define AM79C930_BSS_EIOW 0x04 /* Expand I/O Window */
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#define AM79C930_BSS_TBS 0x03 /* TAI Bank Select */
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#define AM79C930_LMA_LO 2 /* Local Memory Address register (low byte) */
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#define AM79C930_LMA_HI 3 /* Local Memory Address register (high byte) */
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/* set this bit to turn off ISAPnP version */
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#define AM79C930_LMA_HI_ISAPWRDWN 0x80
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/*
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* mmm, inconsistancy in chip documentation:
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* According to page 79--80, all four of the following are equivalent
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* and address the single byte pointed at by BSS_{FS,MBS} | LMA_{HI,LO}
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* According to tables on p63 and p67, they're the LSB through MSB
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* of a 32-bit word.
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*/
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#define AM79C930_IODPA 4 /* I/O Data port A */
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#define AM79C930_IODPB 5 /* I/O Data port B */
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#define AM79C930_IODPC 6 /* I/O Data port C */
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#define AM79C930_IODPD 7 /* I/O Data port D */
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/*
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* Tranceiver Attachment Interface Registers (TIR space)
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* (omitted for now, since host access to them is for diagnostic
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* purposes only).
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*/
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/*
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* memory space goo.
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*/
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#define AM79C930_MEM_SIZE 0x8000 /* 32k */
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#define AM79C930_MEM_BASE 0x0 /* starting at 0 */
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