376 lines
12 KiB
C
376 lines
12 KiB
C
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/**************************************************************************
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Copyright (c) 2007, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Neither the name of the Chelsio Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#include <sys/cdefs.h>
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#ifdef __NetBSD__
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__KERNEL_RCSID(0, "$NetBSD: cxgb_vsc7323.c,v 1.3 2008/01/17 06:03:21 jklos Exp $");
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#endif
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#ifdef __FreeBSD__
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__FBSDID("$FreeBSD: src/sys/dev/cxgb/common/cxgb_vsc7323.c,v 1.3 2007/09/09 01:28:03 kmacy Exp $");
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#endif
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#ifdef CONFIG_DEFINED
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#include <common/cxgb_common.h>
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#else
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#ifdef __FreeBSD__
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#include <dev/cxgb/common/cxgb_common.h>
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#endif
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#ifdef __NetBSD__
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#include "cxgb_common.h"
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#endif
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#endif
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enum {
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ELMR_ADDR = 0,
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ELMR_STAT = 1,
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ELMR_DATA_LO = 2,
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ELMR_DATA_HI = 3,
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ELMR_THRES0 = 0xe000,
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ELMR_BW = 0xe00c,
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ELMR_FIFO_SZ = 0xe00d,
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ELMR_STATS = 0xf000,
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ELMR_MDIO_ADDR = 10
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};
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#define VSC_REG(block, subblock, reg) \
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((reg) | ((subblock) << 8) | ((block) << 12))
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int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n)
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{
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int ret;
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const struct mdio_ops *mo = adapter_info(adap)->mdio_ops;
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ELMR_LOCK(adap);
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ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start);
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for ( ; !ret && n; n--, vals++) {
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ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO,
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*vals & 0xffff);
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if (!ret)
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ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI,
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*vals >> 16);
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}
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ELMR_UNLOCK(adap);
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return ret;
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}
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static int elmr_write(adapter_t *adap, int addr, u32 val)
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{
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return t3_elmr_blk_write(adap, addr, &val, 1);
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}
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int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n)
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{
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int i, ret;
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unsigned int v;
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const struct mdio_ops *mo = adapter_info(adap)->mdio_ops;
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ELMR_LOCK(adap);
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ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start);
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if (ret)
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goto out;
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for (i = 0; i < 5; i++) {
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ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_STAT, &v);
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if (ret)
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goto out;
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if (v == 1)
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break;
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udelay(5);
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}
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if (v != 1) {
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ret = -ETIMEDOUT;
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goto out;
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}
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for ( ; !ret && n; n--, vals++) {
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ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, vals);
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if (!ret) {
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ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI,
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&v);
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*vals |= v << 16;
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}
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}
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out: ELMR_UNLOCK(adap);
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return ret;
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}
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int t3_vsc7323_init(adapter_t *adap, int nports)
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{
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static struct addr_val_pair sys_avp[] = {
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{ VSC_REG(7, 15, 0xf), 2 },
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{ VSC_REG(7, 15, 0x19), 0xd6 },
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{ VSC_REG(7, 15, 7), 0xc },
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{ VSC_REG(7, 1, 0), 0x220 },
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};
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static struct addr_val_pair fifo_avp[] = {
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{ VSC_REG(2, 0, 0x2f), 0 },
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{ VSC_REG(2, 0, 0xf), 0xa0010291 },
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{ VSC_REG(2, 1, 0x2f), 1 },
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{ VSC_REG(2, 1, 0xf), 0xa026301 }
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};
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static struct addr_val_pair xg_avp[] = {
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{ VSC_REG(1, 10, 0), 0x600b },
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{ VSC_REG(1, 10, 1), 0x70600 }, //QUANTA = 96*1024*8/512
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{ VSC_REG(1, 10, 2), 0x2710 },
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{ VSC_REG(1, 10, 5), 0x65 },
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{ VSC_REG(1, 10, 7), 0x23 },
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{ VSC_REG(1, 10, 0x23), 0x800007bf },
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{ VSC_REG(1, 10, 0x23), 0x000007bf },
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{ VSC_REG(1, 10, 0x23), 0x800007bf },
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{ VSC_REG(1, 10, 0x24), 4 }
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};
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int i, ret, ing_step, egr_step, ing_bot, egr_bot;
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for (i = 0; i < ARRAY_SIZE(sys_avp); i++)
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if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr,
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&sys_avp[i].val, 1)))
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return ret;
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ing_step = 0xc0 / nports;
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egr_step = 0x40 / nports;
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ing_bot = egr_bot = 0;
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// ing_wm = ing_step * 64;
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// egr_wm = egr_step * 64;
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/* {ING,EGR}_CONTROL.CLR = 1 here */
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for (i = 0; i < nports; i++) {
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if (
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(ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
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((ing_bot + ing_step) << 16) | ing_bot)) ||
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(ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i),
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0x6000bc0)) ||
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(ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) ||
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(ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i),
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((egr_bot + egr_step) << 16) | egr_bot)) ||
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(ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i),
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0x2000280)) ||
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(ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0)))
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return ret;
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ing_bot += ing_step;
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egr_bot += egr_step;
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}
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for (i = 0; i < ARRAY_SIZE(fifo_avp); i++)
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if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr,
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&fifo_avp[i].val, 1)))
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return ret;
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for (i = 0; i < ARRAY_SIZE(xg_avp); i++)
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if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr,
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&xg_avp[i].val, 1)))
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return ret;
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for (i = 0; i < nports; i++)
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if ((ret = elmr_write(adap, VSC_REG(1, i, 0), 0xa59c)) ||
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(ret = elmr_write(adap, VSC_REG(1, i, 5),
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(i << 12) | 0x63)) ||
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(ret = elmr_write(adap, VSC_REG(1, i, 0xb), 0x96)) ||
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(ret = elmr_write(adap, VSC_REG(1, i, 0x15), 0x21)) ||
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(ret = elmr_write(adap, ELMR_THRES0 + i, 768)))
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return ret;
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if ((ret = elmr_write(adap, ELMR_BW, 7)))
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return ret;
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return ret;
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}
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int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port)
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{
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int mode, clk, r;
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if (speed >= 0) {
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if (speed == SPEED_10)
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mode = clk = 1;
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else if (speed == SPEED_100)
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mode = 1, clk = 2;
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else if (speed == SPEED_1000)
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mode = clk = 3;
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else
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return -EINVAL;
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if ((r = elmr_write(adap, VSC_REG(1, port, 0),
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0xa590 | (mode << 2))) ||
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(r = elmr_write(adap, VSC_REG(1, port, 0xb),
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0x91 | (clk << 1))) ||
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(r = elmr_write(adap, VSC_REG(1, port, 0xb),
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0x90 | (clk << 1))) ||
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(r = elmr_write(adap, VSC_REG(1, port, 0),
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0xa593 | (mode << 2))))
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return r;
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}
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r = (fc & PAUSE_RX) ? 0x60200 : 0x20200; //QUANTA = 32*1024*8/512
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if (fc & PAUSE_TX)
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r |= (1 << 19);
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return elmr_write(adap, VSC_REG(1, port, 1), r);
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}
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int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port)
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{
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return elmr_write(adap, VSC_REG(1, port, 2), mtu);
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}
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int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port)
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{
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int ret;
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ret = elmr_write(adap, VSC_REG(1, port, 3),
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(addr[0] << 16) | (addr[1] << 8) | addr[2]);
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if (!ret)
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ret = elmr_write(adap, VSC_REG(1, port, 4),
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(addr[3] << 16) | (addr[4] << 8) | addr[5]);
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return ret;
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}
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int t3_vsc7323_enable(adapter_t *adap, int port, int which)
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{
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int ret;
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unsigned int v, orig;
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ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1);
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if (!ret) {
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orig = v;
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if (which & MAC_DIRECTION_TX)
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v |= 1;
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if (which & MAC_DIRECTION_RX)
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v |= 2;
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if (v != orig)
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ret = elmr_write(adap, VSC_REG(1, port, 0), v);
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}
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return ret;
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}
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int t3_vsc7323_disable(adapter_t *adap, int port, int which)
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{
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int ret;
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unsigned int v, orig;
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ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1);
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if (!ret) {
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orig = v;
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if (which & MAC_DIRECTION_TX)
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v &= ~1;
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if (which & MAC_DIRECTION_RX)
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v &= ~2;
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if (v != orig)
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ret = elmr_write(adap, VSC_REG(1, port, 0), v);
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}
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return ret;
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}
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#define STATS0_START 1
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#define STATS1_START 0x24
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#define NSTATS0 (0x1d - STATS0_START + 1)
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#define NSTATS1 (0x2a - STATS1_START + 1)
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#define ELMR_STAT(port, reg) (ELMR_STATS + port * 0x40 + reg)
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const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac)
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{
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int ret;
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u64 rx_ucast, tx_ucast;
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u32 stats0[NSTATS0], stats1[NSTATS1];
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ret = t3_elmr_blk_read(mac->adapter,
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ELMR_STAT(mac->ext_port, STATS0_START),
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stats0, NSTATS0);
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if (!ret)
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ret = t3_elmr_blk_read(mac->adapter,
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ELMR_STAT(mac->ext_port, STATS1_START),
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stats1, NSTATS1);
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if (ret)
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goto out;
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/*
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* HW counts Rx/Tx unicast frames but we want all the frames.
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*/
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rx_ucast = mac->stats.rx_frames - mac->stats.rx_mcast_frames -
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mac->stats.rx_bcast_frames;
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rx_ucast += (u64)(stats0[6 - STATS0_START] - (u32)rx_ucast);
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tx_ucast = mac->stats.tx_frames - mac->stats.tx_mcast_frames -
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mac->stats.tx_bcast_frames;
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tx_ucast += (u64)(stats0[27 - STATS0_START] - (u32)tx_ucast);
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#define RMON_UPDATE(mac, name, hw_stat) \
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mac->stats.name += (u64)((hw_stat) - (u32)(mac->stats.name))
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RMON_UPDATE(mac, rx_octets, stats0[4 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames, stats0[6 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames, stats0[7 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames, stats0[8 - STATS0_START]);
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RMON_UPDATE(mac, rx_mcast_frames, stats0[7 - STATS0_START]);
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RMON_UPDATE(mac, rx_bcast_frames, stats0[8 - STATS0_START]);
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RMON_UPDATE(mac, rx_fcs_errs, stats0[9 - STATS0_START]);
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RMON_UPDATE(mac, rx_pause, stats0[2 - STATS0_START]);
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RMON_UPDATE(mac, rx_jabber, stats0[16 - STATS0_START]);
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RMON_UPDATE(mac, rx_short, stats0[11 - STATS0_START]);
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RMON_UPDATE(mac, rx_symbol_errs, stats0[1 - STATS0_START]);
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RMON_UPDATE(mac, rx_too_long, stats0[15 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_64, stats0[17 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_65_127, stats0[18 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_128_255, stats0[19 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_256_511, stats0[20 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_512_1023, stats0[21 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_1024_1518, stats0[22 - STATS0_START]);
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RMON_UPDATE(mac, rx_frames_1519_max, stats0[23 - STATS0_START]);
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RMON_UPDATE(mac, tx_octets, stats0[26 - STATS0_START]);
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RMON_UPDATE(mac, tx_frames, stats0[27 - STATS0_START]);
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RMON_UPDATE(mac, tx_frames, stats0[28 - STATS0_START]);
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RMON_UPDATE(mac, tx_frames, stats0[29 - STATS0_START]);
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RMON_UPDATE(mac, tx_mcast_frames, stats0[28 - STATS0_START]);
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RMON_UPDATE(mac, tx_bcast_frames, stats0[29 - STATS0_START]);
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RMON_UPDATE(mac, tx_pause, stats0[25 - STATS0_START]);
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RMON_UPDATE(mac, tx_underrun, 0);
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RMON_UPDATE(mac, tx_frames_64, stats1[36 - STATS1_START]);
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RMON_UPDATE(mac, tx_frames_65_127, stats1[37 - STATS1_START]);
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RMON_UPDATE(mac, tx_frames_128_255, stats1[38 - STATS1_START]);
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RMON_UPDATE(mac, tx_frames_256_511, stats1[39 - STATS1_START]);
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RMON_UPDATE(mac, tx_frames_512_1023, stats1[40 - STATS1_START]);
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RMON_UPDATE(mac, tx_frames_1024_1518, stats1[41 - STATS1_START]);
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RMON_UPDATE(mac, tx_frames_1519_max, stats1[42 - STATS1_START]);
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#undef RMON_UPDATE
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mac->stats.rx_frames = rx_ucast + mac->stats.rx_mcast_frames +
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mac->stats.rx_bcast_frames;
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mac->stats.tx_frames = tx_ucast + mac->stats.tx_mcast_frames +
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mac->stats.tx_bcast_frames;
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out: return &mac->stats;
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}
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