thorpej e01bd95698 * The Npwr only has 5 interrupt sources, all in XINT3, so don't bother ... reading XINT0 (which isn't even implemented by the CPLD on Npwr). * Adjust the mask of valid IRQ bits for the Npwr.		2002-02-09 03:52:31 +00:00
..
com_obio.c	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00
i80312_mainbus.c	No point in setting the ATU Subsys vendor/dev ID on boards that	2002-02-08 02:31:12 +00:00
iq80310_7seg.c	Some prototype cleanup.	2002-01-20 03:41:47 +00:00
iq80310_intr.c	* The Npwr only has 5 interrupt sources, all in XINT3, so don't bother	2002-02-09 03:52:31 +00:00
iq80310_machdep.c	Default the console to the correct speed on the Npwr (so that	2002-02-08 03:41:56 +00:00
iq80310_pci.c	Wire the internal devices to the right interrupts on NPWR.	2002-02-08 03:28:24 +00:00
iq80310_timer.c	The Npwr has a 19-bit timer. Make sure values programmed into	2002-02-08 23:50:53 +00:00
iq80310reg.h	Remove U from the display seg constants.	2001-12-01 02:02:46 +00:00
iq80310var.h	Add support for the Team ASA Npwr IOP310-based server appliance.	2002-02-07 21:34:23 +00:00
obio_space_asm.S	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00
obio_space.c	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00
obio.c	The Npwr doesn't have the board_rev/cpld_rev/backplane_det registers,	2002-02-08 02:30:12 +00:00
obiovar.h	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00