210 lines
9.0 KiB
C
210 lines
9.0 KiB
C
/* $OpenBSD: if_bwfm_sdio.h,v 1.2 2018/05/19 10:43:10 patrick Exp $ */
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/*
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* Copyright (c) 2010-2016 Broadcom Corporation
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* Copyright (c) 2018 Patrick Wildt <patrick@blueri.se>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/* Registers */
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#define BWFM_SDIO_CCCR_CARDCAP 0xf0
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#define BWFM_SDIO_CCCR_CARDCAP_CMD14_SUPPORT (1 << 1)
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#define BWFM_SDIO_CCCR_CARDCAP_CMD14_EXT (1 << 2)
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#define BWFM_SDIO_CCCR_CARDCAP_CMD_NODEC (1 << 3)
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#define BWFM_SDIO_CCCR_CARDCTRL 0xf1
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#define BWFM_SDIO_CCCR_CARDCTRL_WLANRESET (1 << 1)
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#define BWFM_SDIO_CCCR_SEPINT 0xf2
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#define BWFM_SDIO_CCCR_SEPINT_MASK 0x01
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#define BWFM_SDIO_CCCR_SEPINT_OE (1 << 1)
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#define BWFM_SDIO_CCCR_SEPINT_ACT_HI (1 << 2)
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#define BWFM_SDIO_WATERMARK 0x10008
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#define BWFM_SDIO_DEVICE_CTL 0x10009
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#define BWFM_SDIO_DEVICE_CTL_SETBUSY 0x01
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#define BWFM_SDIO_DEVICE_CTL_SPI_INTR_SYNC 0x02
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#define BWFM_SDIO_DEVICE_CTL_CA_INT_ONLY 0x04
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#define BWFM_SDIO_DEVICE_CTL_PADS_ISO 0x08
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#define BWFM_SDIO_DEVICE_CTL_SB_RST_CTL 0x30
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#define BWFM_SDIO_DEVICE_CTL_RST_CORECTL 0x00
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#define BWFM_SDIO_DEVICE_CTL_RST_BPRESET 0x10
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#define BWFM_SDIO_DEVICE_CTL_RST_NOBPRESET 0x20
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#define BWFM_SDIO_FUNC1_SBADDRLOW 0x1000A
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#define BWFM_SDIO_FUNC1_SBADDRMID 0x1000B
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#define BWFM_SDIO_FUNC1_SBADDRHIGH 0x1000C
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#define BWFM_SDIO_FUNC1_FRAMECTRL 0x1000D
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#define BWFM_SDIO_FUNC1_FRAMECTRL_RF_TERM (1 << 0)
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#define BWFM_SDIO_FUNC1_FRAMECTRL_WF_TERM (1 << 1)
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#define BWFM_SDIO_FUNC1_FRAMECTRL_CRC4WOOS (1 << 2)
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#define BWFM_SDIO_FUNC1_FRAMECTRL_ABORTALL (1 << 3)
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR 0x1000E
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_ALP 0x01
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_HT 0x02
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_ILP 0x04
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL_REQ 0x08
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL_REQ 0x10
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_HW_CLKREQ_OFF 0x20
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL 0x40
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL 0x80
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_CSR_MASK 0x1F
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS \
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(BWFM_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL | \
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BWFM_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL)
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) \
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((regval) & BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS)
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval) \
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(((regval) & BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS) == BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS)
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPONLY(regval) \
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(BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) && \
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!BWFM_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval))
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#define BWFM_SDIO_FUNC1_CHIPCLKCSR_CLKAV(regval, alponly) \
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(BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) && \
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(alponly ? 1 : BWFM_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval)))
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#define BWFM_SDIO_FUNC1_SDIOPULLUP 0x1000F
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#define BWFM_SDIO_FUNC1_WFRAMEBCLO 0x10019
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#define BWFM_SDIO_FUNC1_WFRAMEBCHI 0x1001A
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#define BWFM_SDIO_FUNC1_RFRAMEBCLO 0x1001B
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#define BWFM_SDIO_FUNC1_RFRAMEBCHI 0x1001C
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#define BWFM_SDIO_FUNC1_MESBUSYCTRL 0x1001D
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#define BWFM_SDIO_FUNC1_WAKEUPCTRL 0x1001E
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#define BWFM_SDIO_FUNC1_WAKEUPCTRL_HTWAIT (1 << 1)
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#define BWFM_SDIO_FUNC1_SLEEPCSR 0x1001F
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#define BWFM_SDIO_FUNC1_SLEEPCSR_KSO (1 << 0)
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#define BWFM_SDIO_FUNC1_SLEEPCSR_DEVON (1 << 1)
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#define BWFM_SDIO_SB_OFT_ADDR_PAGE 0x08000
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#define BWFM_SDIO_SB_OFT_ADDR_MASK 0x07FFF
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#define BWFM_SDIO_SB_ACCESS_2_4B_FLAG 0x08000
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/* Protocol defines */
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#define SDPCM_PROT_VERSION 4
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#define SDPCM_PROT_VERSION_SHIFT 16
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#define SDPCM_PROT_VERSION_MASK 0x00ff0000
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#define SDPCM_SHARED_VERSION 0x0003
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#define SDPCM_SHARED_VERSION_MASK 0x00FF
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#define SDPCM_SHARED_ASSERT_BUILT 0x0100
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#define SDPCM_SHARED_ASSERT 0x0200
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#define SDPCM_SHARED_TRAP 0x0400
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#define SDPCMD_INTSTATUS 0x020
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#define SDPCMD_INTSTATUS_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
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#define SDPCMD_INTSTATUS_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
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#define SDPCMD_INTSTATUS_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
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#define SDPCMD_INTSTATUS_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
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#define SDPCMD_INTSTATUS_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
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#define SDPCMD_INTSTATUS_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
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#define SDPCMD_INTSTATUS_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
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#define SDPCMD_INTSTATUS_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
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#define SDPCMD_INTSTATUS_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
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#define SDPCMD_INTSTATUS_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
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#define SDPCMD_INTSTATUS_HMB_FC_STATE SDPCMD_INTSTATUS_HMB_SW0
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#define SDPCMD_INTSTATUS_HMB_FC_CHANGE SDPCMD_INTSTATUS_HMB_SW1
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#define SDPCMD_INTSTATUS_HMB_FRAME_IND SDPCMD_INTSTATUS_HMB_SW2
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#define SDPCMD_INTSTATUS_HMB_HOST_INT SDPCMD_INTSTATUS_HMB_SW3
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#define SDPCMD_INTSTATUS_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
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#define SDPCMD_INTSTATUS_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
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#define SDPCMD_INTSTATUS_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
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#define SDPCMD_INTSTATUS_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
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#define SDPCMD_INTSTATUS_PC (1 << 10)/* descriptor error */
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#define SDPCMD_INTSTATUS_PD (1 << 11)/* data error */
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#define SDPCMD_INTSTATUS_DE (1 << 12)/* Descriptor protocol Error */
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#define SDPCMD_INTSTATUS_RU (1 << 13)/* Receive descriptor Underflow */
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#define SDPCMD_INTSTATUS_RO (1 << 14)/* Receive fifo Overflow */
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#define SDPCMD_INTSTATUS_XU (1 << 15)/* Transmit fifo Underflow */
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#define SDPCMD_INTSTATUS_RI (1 << 16)/* Receive Interrupt */
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#define SDPCMD_INTSTATUS_BUSPWR (1 << 17)/* SDIO Bus Power Change (rev 9) */
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#define SDPCMD_INTSTATUS_XMTDATA_AVAIL (1 << 23)/* bits in fifo */
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#define SDPCMD_INTSTATUS_XI (1 << 24)/* Transmit Interrupt */
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#define SDPCMD_INTSTATUS_RF_TERM (1 << 25)/* Read Frame Terminate */
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#define SDPCMD_INTSTATUS_WF_TERM (1 << 26)/* Write Frame Terminate */
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#define SDPCMD_INTSTATUS_PCMCIA_XU (1 << 27)/* PCMCIA Transmit FIFO Underflow */
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#define SDPCMD_INTSTATUS_SBINT (1 << 28)/* sbintstatus Interrupt */
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#define SDPCMD_INTSTATUS_CHIPACTIVE (1 << 29)/* chip from doze to active state */
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#define SDPCMD_INTSTATUS_SRESET (1 << 30)/* CCCR RES interrupt */
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#define SDPCMD_INTSTATUS_IOE2 (1U << 31)/* CCCR IOE2 Bit Changed */
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#define SDPCMD_INTSTATUS_ERRORS (SDPCMD_INTSTATUS_PC | \
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SDPCMD_INTSTATUS_PD | \
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SDPCMD_INTSTATUS_DE | \
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SDPCMD_INTSTATUS_RU | \
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SDPCMD_INTSTATUS_RO | \
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SDPCMD_INTSTATUS_XU)
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#define SDPCMD_INTSTATUS_DMA (SDPCMD_INTSTATUS_RI | \
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SDPCMD_INTSTATUS_XI | \
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SDPCMD_INTSTATUS_ERRORS)
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#define SDPCMD_HOSTINTMASK 0x024
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#define SDPCMD_INTMASK 0x028
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#define SDPCMD_SBINTSTATUS 0x02c
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#define SDPCMD_SBINTMASK 0x030
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#define SDPCMD_FUNCTINTMASK 0x034
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#define SDPCMD_TOSBMAILBOX 0x040
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#define SDPCMD_TOSBMAILBOX_NAK (1 << 0)
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#define SDPCMD_TOSBMAILBOX_INT_ACK (1 << 1)
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#define SDPCMD_TOSBMAILBOX_USE_OOB (1 << 2)
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#define SDPCMD_TOSBMAILBOX_DEV_INT (1 << 3)
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#define SDPCMD_TOHOSTMAILBOX 0x044
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#define SDPCMD_TOSBMAILBOXDATA 0x048
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#define SDPCMD_TOHOSTMAILBOXDATA 0x04C
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#define SDPCMD_TOHOSTMAILBOXDATA_NAKHANDLED (1 << 0)
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#define SDPCMD_TOHOSTMAILBOXDATA_DEVREADY (1 << 1)
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#define SDPCMD_TOHOSTMAILBOXDATA_FC (1 << 2)
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#define SDPCMD_TOHOSTMAILBOXDATA_FWREADY (1 << 3)
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#define SDPCMD_TOHOSTMAILBOXDATA_FWHALT (1 << 4)
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struct bwfm_sdio_hwhdr {
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uint16_t frmlen;
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uint16_t cksum;
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};
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struct bwfm_sdio_hwexthdr {
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uint16_t pktlen;
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uint8_t res0;
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uint8_t flags;
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uint16_t res1;
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uint16_t padlen;
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};
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struct bwfm_sdio_swhdr {
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uint8_t seqnr;
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uint8_t chanflag; /* channel + flag */
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#define BWFM_SDIO_SWHDR_CHANNEL_CONTROL 0x00
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#define BWFM_SDIO_SWHDR_CHANNEL_EVENT 0x01
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#define BWFM_SDIO_SWHDR_CHANNEL_DATA 0x02
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#define BWFM_SDIO_SWHDR_CHANNEL_GLOM 0x03
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#define BWFM_SDIO_SWHDR_CHANNEL_TEST 0x0F
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#define BWFM_SDIO_SWHDR_CHANNEL_MASK 0x0F
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uint8_t nextlen;
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uint8_t dataoff;
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uint8_t flowctl;
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uint8_t maxseqnr;
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uint16_t res0;
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};
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struct bwfm_sdio_sdpcm {
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uint32_t flags;
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uint32_t trap_addr;
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uint32_t assert_exp_addr;
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uint32_t assert_file_addr;
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uint32_t assert_line;
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uint32_t console_addr;
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uint32_t msgtrace_addr;
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uint8_t tag[32];
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uint32_t brpt_addr;
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};
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struct bwfm_sdio_console {
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uint32_t vcons_in;
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uint32_t vcons_out;
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uint32_t log_buf;
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uint32_t log_bufsz;
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uint32_t log_idx;
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};
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