124 lines
5.2 KiB
C
124 lines
5.2 KiB
C
/* $NetBSD: sqphyreg.h,v 1.5 2008/04/28 20:23:53 martin Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_SQPHYREG_H_
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#define _DEV_MII_SQPHYREG_H_
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/*
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* Seeq 80220 registers. This also covers the Seeq 80225, which is
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* a stripped-down-for-lower-power-consumption version of the 80223.
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* It only has a STATUS register, and only the SPD_DET and DPLX_DET
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* bits are valid.
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*/
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#define MII_SQPHY_CONFIG1 0x10 /* Configuration 1 Register */
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#define CONFIG1_LNK_DIS 0x8000 /* Link Detect Disable */
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#define CONFIG1_XMT_DIS 0x4000 /* TP Transmitter Disable */
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#define CONFIG1_XMT_PDN 0x2000 /* TP Transmitter Powerdown */
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#define CONFIG1_TXEN_CRS 0x1000 /* TX_EN to CRS Loopback Disable */
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#define CONFIG1_BYP_ENC 0x0800 /* Bypass Encoder */
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#define CONFIG1_BYP_SCR 0x0400 /* Bypass Scrambler */
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#define CONFIG1_UNSCR_DIS 0x0200 /* Unscr. Idle Reception Disable */
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#define CONFIG1_EQLZR 0x0100 /* Rx Equalizer Disable */
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#define CONFIG1_CABLE 0x0080 /* Cable: 1 = STP, 0 = UTP */
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#define CONFIG1_RLVL0 0x0040 /* Receive Level Adjust */
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#define CONFIG1_TLVL3 0x0020 /* Transmit output level adjust */
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#define CONFIG1_TLVL2 0x0010
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#define CONFIG1_TLVL1 0x0008
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#define CONFIG1_TLVL0 0x0004
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#define CONFIG1_TRF1 0x0002 /* Transmitter Rise/Fall Adjust */
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#define CONFIG1_TRF0 0x0001
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#define MII_SQPHY_CONFIG2 0x11 /* Configuration 2 Register */
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#define CONFIG2_PLED3_1 0x8000 /* PLED3 configuration */
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#define CONFIG2_PLED3_0 0x4000
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/* 1 1 LINK100 (default) */
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/* 1 0 Blink */
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/* 0 1 On */
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/* 0 0 Off */
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#define CONFIG2_PLED2_1 0x2000 /* PLED2 configuration */
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#define CONFIG2_PLED2_0 0x1000
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/* 1 1 Activity (default) */
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/* 1 0 Blink */
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/* 0 1 On */
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/* 0 0 Off */
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#define CONFIG2_PLED1_1 0x0800 /* PLED1 configuration */
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#define CONFIG2_PLED1_0 0x0400
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/* 1 1 Full duplex (default) */
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/* 1 0 Blink */
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/* 0 1 On */
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/* 0 0 Off */
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#define CONFIG2_PLED0_1 0x0200 /* PLED0 configuration */
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#define CONFIG2_PLED0_0 0x0100
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/* 1 1 LINK10 (default) */
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/* 1 0 Blink */
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/* 0 1 On */
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/* 0 0 Off */
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#define CONFIG2_LED_DEF1 0x0080 /* LED Normal Function Select */
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#define CONFIG2_LED_DEF0 0x0040
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#define CONFIG2_APOL_DIS 0x0020 /* Auto Polarity Correct Disable */
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#define CONFIG2_JAB_DIS 0x0010 /* Jabber Disable */
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#define CONFIG2_MREG 0x0008 /* Multiple Register Access Enable */
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#define CONFIG2_INT_MDIO 0x0004 /* MDIO Interrupt when idle */
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#define CONFIG2_RJ_CFG 0x0002 /* R/J Configuration Select */
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#define MII_SQPHY_STATUS 0x12 /* Status Output Register */
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#define STATUS_INT 0x8000 /* Interrupt Detect */
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#define STATUS_LNK_FAIL 0x4000 /* Link Fail */
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#define STATUS_LOSS_SYNC 0x2000 /* Descrambler lost synchronization */
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#define STATUS_CWRD 0x1000 /* Codeword Error */
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#define STATUS_SSD 0x0800 /* Start of Stream Error */
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#define STATUS_ESD 0x0400 /* End of Stream Error */
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#define STATUS_RPOL 0x0200 /* Reverse Polarity Detected */
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#define STATUS_JAB 0x0100 /* Jabber Detected */
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#define STATUS_SPD_DET 0x0080 /* 100Mbps */
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#define STATUS_DPLX_DET 0x0040 /* Full Duplex */
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#define MII_SQPHY_MASK 0x13 /* Mask Register */
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#define MASK_INT 0x8000 /* mask INT */
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#define MASK_LNK_FAIL 0x4000 /* mask LNK_FAIL */
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#define MASK_LOSS_SYNC 0x2000 /* mask LOSS_SYNC */
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#define MASK_CWRD 0x1000 /* mask CWRD */
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#define MASK_SSD 0x0800 /* mask SSD */
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#define MASK_ESD 0x0400 /* mask ESD */
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#define MASK_RPOL 0x0200 /* mask RPOL */
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#define MASK_JAB 0x0100 /* mask JAB */
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#define MASK_SPD_DET 0x0080 /* mask SPD_DET */
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#define MASK_DPLX_DET 0x0040 /* mask DPLX_DET */
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#define MASK_ANEG_STS1 0x0020 /* mask ANEG_STS1 */
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#define MASK_ANEG_STS0 0x0010 /* mask ANEG_STS0 */
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#define MII_SQPHY_RESERVED 0x14 /* Reserved Register */
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/* All bits must be 0 */
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#endif /* _DEV_MII_SQPHYREG_H_ */
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