354 lines
10 KiB
C
354 lines
10 KiB
C
/* $NetBSD: mvphy.c,v 1.15 2020/03/15 23:04:50 thorpej Exp $ */
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/*-
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* Copyright (c) 2006 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Driver for Marvell 88E6060 10/100 5-port PHY switch.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mvphy.c,v 1.15 2020/03/15 23:04:50 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/mvphyreg.h>
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#define MV_PORT(sc) ((sc)->mii_phy - 16) /* PHY # to switch port */
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#define MV_CPU_PORT 5 /* port # of CPU port */
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#define MV_READ(p, phy, r, v) \
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(*(p)->mii_pdata->mii_readreg)(device_parent((p)->mii_dev), \
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(phy), (r), (v))
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#define MV_WRITE(p, phy, r, v) \
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(*(p)->mii_pdata->mii_writereg)(device_parent((p)->mii_dev), \
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(phy), (r), (v))
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/* XXX sysctl'able */
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#define MV_ATUCTRL_ATU_SIZE_DEFAULT 2 /* 1024 entry database */
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#define MV_ATUCTRL_AGE_TIME_DEFAULT 19 /* 19 * 16 = 304 seconds */
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/*
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* Register manipulation macros that expect bit field defines
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* to follow the convention that an _S suffix is appended for
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* a shift count, while the field mask has no suffix.
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*/
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#define SM(_v, _f) (((_v) << _f##_S) & _f)
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#define MS(_v, _f) (((_v) & _f) >> _f##_S)
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static int mvphymatch(device_t, cfdata_t, void *);
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static void mvphyattach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(mvphy, sizeof(struct mii_softc),
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mvphymatch, mvphyattach, mii_phy_detach, mii_phy_activate);
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static int mvphy_service(struct mii_softc *, struct mii_data *, int);
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static void mvphy_status(struct mii_softc *);
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static void mvphy_reset(struct mii_softc *sc);
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static const struct mii_phy_funcs mvphy_funcs = {
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mvphy_service, mvphy_status, mvphy_reset,
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};
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static const struct mii_phydesc mvphys[] = {
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MII_PHY_DESC(xxMARVELL, E6060),
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MII_PHY_END,
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};
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/*
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* On AP30/AR5312 the switch is configured in one of two ways:
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* as a ROUTER or as a BRIDGE. The ROUTER config sets up ports
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* 0-3 as LAN ports, port 4 as the WAN port, and port 5 connects
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* to the MAC in the 5312. The BRIDGE config sets up ports
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* 0-4 as LAN ports with port 5 connected to the MAC in the 5312.
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*/
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struct mvPhyConfig {
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uint16_t switchPortAddr;/* switch port associated with PHY */
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uint16_t vlanSetting; /* VLAN table setting for PHY */
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uint32_t portControl; /* switch port control setting for PHY */
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};
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static const struct mvPhyConfig dumbConfig[] = {
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{ 0x18, 0x2e, /* PHY port 0 = LAN port 0 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x19, 0x2d, /* PHY port 1 = LAN port 1 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1a, 0x2b, /* PHY port 2 = LAN port 2 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1b, 0x27, /* PHY port 3 = LAN port 3 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1c, 0x25, /* PHY port 4 = LAN port 4 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1d, 0x1f, /* PHY port 5 = CPU port */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING }
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};
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#if 0 /* XXX what are these? */
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static const struct mvPhyConfig routerConfig[] = {
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{ 0x18, 0x2e, /* PHY port 0 = LAN port 0 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x19, 0x2d, /* PHY port 1 = LAN port 1 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1a, 0x2b, /* PHY port 2 = LAN port 2 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1b, 0x27, /* PHY port 3 = LAN port 3 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1c, 0x1020, /* PHY port 4 = WAN port */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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/* NB: 0x0f =>'s send only to LAN ports */
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{ 0x1d, 0x0f, /* PHY port 5 = CPU port */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING
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#if 0
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| MV_PORT_CONTROL_INGRESS_TRAILER
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| MV_PORT_CONTROL_EGRESS_MODE
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#endif
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}
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};
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static const struct mvPhyConfig bridgeConfig[] = {
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{ 0x18, 0x3e, /* PHY port 0 = LAN port 0 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x19, 0x3d, /* PHY port 1 = LAN port 1 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1a, 0x3b, /* PHY port 2 = LAN port 2 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1b, 0x37, /* PHY port 3 = LAN port 3 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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{ 0x1c, 0x37, /* PHY port 4 = LAN port 4 */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING },
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/* NB: 0x1f =>'s send to all ports */
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{ 0x1d, 0x1f, /* PHY port 5 = CPU port */
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MV_PORT_CONTROL_PORT_STATE_FORWARDING
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#if 0
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| MV_PORT_CONTROL_INGRESS_TRAILER
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| MV_PORT_CONTROL_EGRESS_MODE
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#endif
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}
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};
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#endif
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static void mvphy_switchconfig(struct mii_softc *, int);
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static void mvphy_flushatu(struct mii_softc *);
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static int
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mvphymatch(device_t parent, cfdata_t match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, mvphys) != NULL)
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return 10;
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return 0;
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}
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static void
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mvphyattach(device_t parent, device_t self, void *aux)
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{
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struct mii_softc *sc = device_private(self);
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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mpd = mii_phy_match(ma, mvphys);
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aprint_naive(": Media interface\n");
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
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sc->mii_dev = self;
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_funcs = &mvphy_funcs;
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sc->mii_pdata = mii;
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sc->mii_flags = ma->mii_flags;
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mii_lock(mii);
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if (MV_PORT(sc) == 0) { /* NB: only when attaching first PHY */
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/*
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* Set the global switch settings and configure the
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* CPU port since it does not probe as a visible PHY.
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*/
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MV_WRITE(sc, MII_MV_SWITCH_GLOBAL_ADDR, MV_ATU_CONTROL,
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SM(MV_ATUCTRL_AGE_TIME_DEFAULT, MV_ATUCTRL_AGE_TIME)
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| SM(MV_ATUCTRL_ATU_SIZE_DEFAULT, MV_ATUCTRL_ATU_SIZE));
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mvphy_switchconfig(sc, MV_CPU_PORT);
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}
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PHY_RESET(sc);
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PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
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sc->mii_capabilities &= ma->mii_capmask;
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mii_unlock(mii);
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mii_phy_add_media(sc);
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}
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static int
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mvphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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KASSERT(mii_locked(mii));
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switch (cmd) {
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case MII_POLLSTAT:
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/* If we're not polling our PHY instance, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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/* XXX? */
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return 0;
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}
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/* If the interface is not up, don't do anything. */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
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/* If we're not currently selected, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return 0;
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break;
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case MII_DOWN:
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mii_phy_down(sc);
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return 0;
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}
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/* Update the media status. */
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mii_phy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return 0;
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}
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static void
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mvphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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uint16_t hwstatus;
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KASSERT(mii_locked(mii));
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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PHY_READ(sc, MII_MV_PHY_SPECIFIC_STATUS, &hwstatus);
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if (hwstatus & MV_STATUS_REAL_TIME_LINK_UP) {
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mii->mii_media_status |= IFM_ACTIVE;
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if (hwstatus & MV_STATUS_RESOLVED_SPEED_100)
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mii->mii_media_active |= IFM_100_TX;
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else
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mii->mii_media_active |= IFM_10_T;
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if (hwstatus & MV_STATUS_RESOLVED_DUPLEX_FULL)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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} else {
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mii->mii_media_active |= IFM_NONE;
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/* XXX flush ATU only on link down transition */
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mvphy_flushatu(sc);
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}
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}
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static void
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mvphy_reset(struct mii_softc *sc)
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{
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KASSERT(mii_locked(sc->mii_pdata));
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/* XXX handle fixed media config */
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PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN);
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mvphy_switchconfig(sc, MV_PORT(sc));
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}
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/*
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* Configure switch for the specified port.
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*/
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static void
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mvphy_switchconfig(struct mii_softc *sc, int port)
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{
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/* XXX router vs bridge */
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/*const struct mvPhyConfig *conf = &routerConfig[port];*/
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/*const struct mvPhyConfig *conf = &bridgeConfig[port];*/
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const struct mvPhyConfig *conf = &dumbConfig[port];
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MV_WRITE(sc, conf->switchPortAddr, MV_PORT_BASED_VLAN_MAP,
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conf->vlanSetting);
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/* XXX administrative control of port enable? */
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MV_WRITE(sc, conf->switchPortAddr, MV_PORT_CONTROL, conf->portControl);
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MV_WRITE(sc, conf->switchPortAddr, MV_PORT_ASSOCIATION_VECTOR,
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1 << port);
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}
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/*
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* Flush the Address Translation Unit (ATU).
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*/
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static void
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mvphy_flushatu(struct mii_softc *sc)
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{
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int status;
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uint16_t reg;
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int i;
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/* wait for any previous request to complete */
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/* XXX if busy defer to tick */
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/* XXX timeout */
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for (i = 0; i < 1000; i++) {
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status = MV_READ(sc, MII_MV_SWITCH_GLOBAL_ADDR,
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MV_ATU_OPERATION, ®);
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if (MV_ATU_IS_BUSY(status))
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break;
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}
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if (i != 1000) {
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MV_WRITE(sc, MII_MV_SWITCH_GLOBAL_ADDR, MV_ATU_OPERATION,
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MV_ATU_OP_FLUSH_ALL | MV_ATU_BUSY);
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} /*else
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aprint_error_dev(sc->mii_dev, "timeout waiting for ATU flush\n");*/
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}
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