495 lines
13 KiB
C
495 lines
13 KiB
C
/* $NetBSD: atphy.c,v 1.31 2023/02/22 08:09:09 msaitoh Exp $ */
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/* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */
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/*-
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* Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Driver for the Attansic F1 10/100/1000 PHY.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.31 2023/02/22 08:09:09 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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/* Special Control Register */
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#define ATPHY_SCR 0x10
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#define ATPHY_SCR_JABBER_DISABLE 0x0001
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#define ATPHY_SCR_POLARITY_REVERSAL 0x0002
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#define ATPHY_SCR_SQE_TEST 0x0004
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#define ATPHY_SCR_MAC_PDOWN 0x0008
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#define ATPHY_SCR_CLK125_DISABLE 0x0010
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#define ATPHY_SCR_MDI_MANUAL_MODE 0x0000
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#define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020
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#define ATPHY_SCR_AUTO_X_1000T 0x0040
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#define ATPHY_SCR_AUTO_X_MODE 0x0060
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#define ATPHY_SCR_10BT_EXT_ENABLE 0x0080
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#define ATPHY_SCR_MII_5BIT_ENABLE 0x0100
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#define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200
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#define ATPHY_SCR_FORCE_LINK_GOOD 0x0400
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#define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800
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/* Special Status Register. */
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#define ATPHY_SSR 0x11
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#define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800
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#define ATPHY_SSR_DUPLEX 0x2000
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#define ATPHY_SSR_SPEED_MASK 0xC000
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#define ATPHY_SSR_10MBS 0x0000
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#define ATPHY_SSR_100MBS 0x4000
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#define ATPHY_SSR_1000MBS 0x8000
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#define ATPHY_DEBUG_PORT_ADDR 0x1d
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#define ATPHY_DEBUG_PORT_DATA 0x1e
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#define ATPHY_RGMII_RX_CLK_DLY __BIT(15)
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#define ATPHY_RGMII_TX_CLK_DLY __BIT(8)
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static int atphy_match(device_t, cfdata_t, void *);
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static void atphy_attach(device_t, device_t, void *);
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static int atphy_service(struct mii_softc *, struct mii_data *, int);
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static void atphy_reset(struct mii_softc *);
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static void atphy_status(struct mii_softc *);
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static int atphy_mii_phy_auto(struct mii_softc *);
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static bool atphy_is_gige(const struct mii_phydesc *);
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struct atphy_softc {
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struct mii_softc mii_sc;
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int mii_clk_25m;
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bool rgmii_tx_internal_delay;
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bool rgmii_rx_internal_delay;
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};
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CFATTACH_DECL_NEW(atphy, sizeof(struct atphy_softc),
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atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate);
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const struct mii_phy_funcs atphy_funcs = {
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atphy_service, atphy_status, atphy_reset,
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};
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static const struct mii_phydesc atphys[] = {
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MII_PHY_DESC(ATTANSIC, L1),
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MII_PHY_DESC(ATTANSIC, L2),
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MII_PHY_DESC(ATTANSIC, AR8021),
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MII_PHY_DESC(ATTANSIC, AR8035),
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MII_PHY_END,
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};
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static void
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atphy_clk_25m(struct atphy_softc *asc)
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{
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struct mii_softc *sc = &asc->mii_sc;
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struct {
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uint32_t hz;
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uint16_t data;
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} select_clk[] = {
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{ 25000000, 0x0 },
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{ 50000000, 0x1 },
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{ 62500000, 0x2 },
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{ 125000000, 0x3 }
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};
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uint16_t data = 0;
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uint16_t reg = 0;
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for (int i = 0; i < __arraycount(select_clk); i++) {
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if (asc->mii_clk_25m <= select_clk[i].hz)
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data = select_clk[i].data;
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}
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PHY_WRITE(sc, 0x0d, 0x0007);
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PHY_WRITE(sc, 0x0e, 0x8016);
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PHY_WRITE(sc, 0x0d, 0x4007);
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PHY_READ(sc, 0x0e, ®);
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PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3)));
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}
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static bool
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atphy_is_gige(const struct mii_phydesc *mpd)
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{
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switch (mpd->mpd_oui) {
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case MII_OUI_ATTANSIC:
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switch (mpd->mpd_model) {
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case MII_MODEL_ATTANSIC_L2:
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return false;
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}
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}
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return true;
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}
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static int
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atphy_match(device_t parent, cfdata_t match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, atphys) != NULL)
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return 10;
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return 0;
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}
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void
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atphy_attach(device_t parent, device_t self, void *aux)
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{
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struct atphy_softc *asc = device_private(self);
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prop_dictionary_t parent_prop = device_properties(parent);
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prop_dictionary_t prop = device_properties(self);
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struct mii_softc *sc = &asc->mii_sc;
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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uint16_t bmsr;
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mpd = mii_phy_match(ma, atphys);
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aprint_naive(": Media interface\n");
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
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sc->mii_dev = self;
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
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sc->mii_mpd_rev = MII_REV(ma->mii_id2);
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sc->mii_funcs = &atphy_funcs;
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sc->mii_pdata = mii;
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sc->mii_flags = ma->mii_flags;
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sc->mii_flags |= MIIF_NOLOOP;
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prop_dictionary_get_bool(parent_prop, "tx_internal_delay",
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&asc->rgmii_tx_internal_delay);
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prop_dictionary_get_bool(parent_prop, "rx_internal_delay",
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&asc->rgmii_rx_internal_delay);
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prop_dictionary_get_uint32(prop, "clk_25m", &asc->mii_clk_25m);
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if (asc->mii_clk_25m != 0)
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atphy_clk_25m(asc);
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mii_lock(mii);
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PHY_RESET(sc);
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PHY_READ(sc, MII_BMSR, &bmsr);
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PHY_READ(sc, MII_BMSR, &bmsr);
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sc->mii_capabilities = bmsr & ma->mii_capmask;
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if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT))
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PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
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mii_unlock(mii);
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mii_phy_add_media(sc);
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}
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int
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atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t anar, bmcr, bmsr;
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KASSERT(mii_locked(mii));
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switch (cmd) {
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case MII_POLLSTAT:
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/* If we're not polling our PHY instance, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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PHY_READ(sc, MII_BMCR, &bmcr);
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
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return 0;
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}
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/* If the interface is not up, don't do anything. */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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bmcr = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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case IFM_1000_T:
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atphy_mii_phy_auto(sc);
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goto done;
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case IFM_100_TX:
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bmcr = BMCR_S100;
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break;
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case IFM_10_T:
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bmcr = BMCR_S10;
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break;
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case IFM_NONE:
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PHY_READ(sc, MII_BMCR, &bmcr);
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/*
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* XXX
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* Due to an unknown reason powering down PHY resulted
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* in unexpected results such as inaccessibility of
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* hardware of freshly rebooted system. Disable
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* powering down PHY until I got more information for
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* Attansic/Atheros PHY hardwares.
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*/
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
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goto done;
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default:
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return EINVAL;
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}
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anar = mii_anar(ife);
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if ((ife->ifm_media & IFM_FDX) != 0) {
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bmcr |= BMCR_FDX;
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/* Enable pause. */
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if (sc->mii_flags & MIIF_DOPAUSE)
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anar |= ANAR_PAUSE_TOWARDS;
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}
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if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
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EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, MII_100T2CR, 0);
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PHY_WRITE(sc, MII_ANAR, anar);
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/* Start autonegotiation. */
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
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done:
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break;
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case MII_TICK:
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/* If we're not currently selected, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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/* Is the interface even up? */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return 0;
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/* Only used for autonegotiation. */
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if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
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(IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
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sc->mii_ticks = 0;
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break;
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}
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/*
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* Check for link.
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* Read the status register twice; BMSR_LINK is latch-low.
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*/
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PHY_READ(sc, MII_BMSR, &bmsr);
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PHY_READ(sc, MII_BMSR, &bmsr);
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if (bmsr & BMSR_LINK) {
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sc->mii_ticks = 0;
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break;
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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/* Only retry autonegotiation every mii_anegticks seconds. */
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if (sc->mii_ticks < sc->mii_anegticks)
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break;
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atphy_mii_phy_auto(sc);
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break;
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}
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/* Update the media status. */
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mii_phy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return 0;
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}
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static void
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atphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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uint16_t bmsr, bmcr, gsr, ssr;
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KASSERT(mii_locked(mii));
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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PHY_READ(sc, MII_BMSR, &bmsr);
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PHY_READ(sc, MII_BMSR, &bmsr);
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if (bmsr & BMSR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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PHY_READ(sc, MII_BMCR, &bmcr);
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if (bmcr & BMCR_ISO) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if (bmcr & BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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PHY_READ(sc, ATPHY_SSR, &ssr);
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if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch (ssr & ATPHY_SSR_SPEED_MASK) {
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case ATPHY_SSR_1000MBS:
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mii->mii_media_active |= IFM_1000_T;
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/*
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* atphy(4) has a valid link so reset mii_ticks.
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* Resetting mii_ticks is needed in order to
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* detect link loss after auto-negotiation.
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*/
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sc->mii_ticks = 0;
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break;
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case ATPHY_SSR_100MBS:
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mii->mii_media_active |= IFM_100_TX;
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sc->mii_ticks = 0;
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break;
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case ATPHY_SSR_10MBS:
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mii->mii_media_active |= IFM_10_T;
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sc->mii_ticks = 0;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if (ssr & ATPHY_SSR_DUPLEX)
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mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
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else
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mii->mii_media_active |= IFM_HDX;
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PHY_READ(sc, MII_100T2SR, &gsr);
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if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
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gsr & GTSR_MS_RES)
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mii->mii_media_active |= IFM_ETH_MASTER;
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}
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static void
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atphy_reset(struct mii_softc *sc)
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{
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struct atphy_softc *asc = (struct atphy_softc *)sc;
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uint16_t reg;
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int i;
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KASSERT(mii_locked(sc->mii_pdata));
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/*
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* Take PHY out of power down mode.
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*
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* XXX AR8021 document has no description about the power saving
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* control register. Shouldn't we write it?
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*/
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PHY_WRITE(sc, 29, 0x29);
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/*
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* XXX AR8031 document says the lower 14 bits are reserved and the
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* default value is 0x36d0. Shouldn't we clear those bits?
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* I have no document neither L1(F1) nor L2(F2).
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*/
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PHY_WRITE(sc, 30, 0);
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if ((sc->mii_mpd_model == MII_MODEL_ATTANSIC_L2)
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&& (sc->mii_mpd_rev == 1)) {
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/*
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* On NVIDIA MCP61 with Attansic L2 rev. 1, changing debug
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* port 0x29's value makes the next PHY read fail with error.
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* This is observed on ASUS M2N-MX SE Plus. Read any register
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* to ignore this problem.
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*/
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(void)PHY_READ(sc, ATPHY_SCR, ®);
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}
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PHY_READ(sc, ATPHY_SCR, ®);
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/* Enable automatic crossover. */
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reg |= ATPHY_SCR_AUTO_X_MODE;
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/* Disable power down. */
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reg &= ~ATPHY_SCR_MAC_PDOWN;
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/* Enable CRS on Tx. */
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reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
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/* Auto correction for reversed cable polarity. */
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reg |= ATPHY_SCR_POLARITY_REVERSAL;
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PHY_WRITE(sc, ATPHY_SCR, reg);
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atphy_mii_phy_auto(sc);
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/* Workaround F1 bug to reset phy. */
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PHY_READ(sc, MII_BMCR, ®);
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reg |= BMCR_RESET;
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PHY_WRITE(sc, MII_BMCR, reg);
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for (i = 0; i < 1000; i++) {
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DELAY(1);
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PHY_READ(sc, MII_BMCR, ®);
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if ((reg & BMCR_RESET) == 0)
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break;
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}
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if (asc->rgmii_tx_internal_delay) {
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PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x05);
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PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_TX_CLK_DLY);
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}
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if (asc->rgmii_rx_internal_delay) {
|
|
PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x00);
|
|
PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_RX_CLK_DLY);
|
|
}
|
|
}
|
|
|
|
static int
|
|
atphy_mii_phy_auto(struct mii_softc *sc)
|
|
{
|
|
uint16_t anar;
|
|
|
|
KASSERT(mii_locked(sc->mii_pdata));
|
|
|
|
sc->mii_ticks = 0;
|
|
anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
|
|
if (sc->mii_flags & MIIF_DOPAUSE)
|
|
anar |= ANAR_PAUSE_TOWARDS;
|
|
PHY_WRITE(sc, MII_ANAR, anar);
|
|
if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
|
|
PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
|
|
GTCR_ADV_1000THDX);
|
|
PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
|
|
|
|
return EJUSTRETURN;
|
|
}
|