867 lines
35 KiB
C
867 lines
35 KiB
C
/* $NetBSD: mvgbereg.h,v 1.10 2024/02/02 22:39:10 andvar Exp $ */
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/*
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* Copyright (c) 2007, 2013 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVGBEREG_H_
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#define _MVGBEREG_H_
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/*
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* For ARMEB, peripheral is configured to little-endian mode, even if
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* CPU itself is in big-endian mode...
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*/
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#if BYTE_ORDER == BIG_ENDIAN && !defined(__arm__)
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#define MVGBE_BIG_ENDIAN
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#endif
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/*
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* ... therefore, we need byte-swapping descriptor fields.
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*/
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#if BYTE_ORDER == BIG_ENDIAN && defined(__arm__)
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#define H2MVGBE16(x) htole16(x)
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#define H2MVGBE32(x) htole32(x)
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#define MVGBE2H16(x) le16toh(x)
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#define MVGBE2H32(x) le32toh(x)
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#else
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#define H2MVGBE16(x) (x)
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#define H2MVGBE32(x) (x)
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#define MVGBE2H16(x) (x)
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#define MVGBE2H32(x) (x)
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#endif
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#define MVGBE_SIZE 0x4000
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#define MVGBE_NWINDOW 6
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#define MVGBE_NREMAP 4
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#define MVGBE_PHY_TIMEOUT 10000 /* msec */
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/*
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* Ethernet Unit Registers
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*/
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#define MVGBE_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
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#define MVGBE_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
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#define MVGBE_PRXF01(q) (0x1440 + ((q) << 2)) /* Port RX Prefetch 0_1 */
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#define MVGBE_PRXF23(q) (0x1460 + ((q) << 2)) /* Port RX Prefetch 2_3 */
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#define MVGBE_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/
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#define MVGBE_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/
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#define MVGBE_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/
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#define MVGBE_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
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#define MVGBE_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/
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#define MVGBE_PPLBSZ(q) (0x1700 + ((q) << 2)) /* P Pool n Buffer Size */
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#define MVGBE_PRXFC 0x1710 /* Port RX Flow Control */
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#define MVGBE_PRXTXP 0x1714 /* Port RX_TX Pause */
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#define MVGBE_PRXFCG 0x1718 /* Port RX Flow Control Generation */
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#define MVGBE_PRXINIT 0x1cc0 /* Port RX Initialization */
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#define MVGBE_RXCTRL 0x1d00 /* RX Control */
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#define MVGBE_RXHWFWD(n) (0x1d10 + (((n) & ~0x1) << 1))
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/* RX Hardware Forwarding (0_1, 2_3,..., 8_9) */
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#define MVGBE_RXHWFWDPTR 0x1d30 /* RX Hardware Forwarding Pointer */
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#define MVGBE_RXHWFWDTH 0x1d40 /* RX Hardware Forwarding Threshold */
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#define MVGBE_RXHWFWDDQA 0x1d44 /* RX Hw Fwd Descriptors Queue Address*/
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#define MVGBE_RXHWFWDQS 0x1d48 /* RX Hw Fwd Descriptors Queue Size */
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#define MVGBE_RXHWFWDQENB 0x1d4c /* RX Hw Fwd Queue Enable */
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#define MVGBE_RXHWFWDACPT 0x1d50 /* RX Hw Forwarding Accepted Counter */
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#define MVGBE_RXHWFWDYDSCRD 0x1d54 /* RX Hw Fwd Yellow Discarded Counter */
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#define MVGBE_RXHWFWDGDSCRD 0x1d58 /* RX Hw Fwd Green Discarded Counter */
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#define MVGBE_RXHWFWDTHDSCRD 0x1d5c /*RX HwFwd Threshold Discarded Counter*/
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#define MVGBE_RXHWFWDTXGAP 0x1d6c /*RX Hardware Forwarding TX Access Gap*/
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/* Ethernet Unit Global Registers */
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#define MVGBE_PHYADDR 0x2000
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#if defined(MV88W8660)
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#define MVGBE_SMI 0x8010
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#else
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#define MVGBE_SMI 0x2004
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#endif
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#define MVGBE_EUDA 0x2008 /* Ethernet Unit Default Address */
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#define MVGBE_EUDID 0x200c /* Ethernet Unit Default ID */
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#define MVGBE_EU 0x2014 /* Ethernet Unit Reserved */
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#define MVGBE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */
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#define MVGBE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */
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#define MVGBE_EUEA 0x2094 /* Ethernet Unit Error Address */
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#define MVGBE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */
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#define MVGBE_EUPCR 0x20a0 /* EthernetUnit Port Pads Calibration */
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#define MVGBE_EUC 0x20b0 /* Ethernet Unit Control */
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#define MVGBE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
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#define MVGBE_S(n) (0x2204 + ((n) << 3)) /* Size */
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#define MVGBE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
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#define MVGBE_BARE 0x2290 /* Base Address Enable */
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#define MVGBE_EPAP 0x2294 /* Ethernet Port Access Protect */
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/* Ethernet Unit Port Registers */
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#define MVGBE_PORTR_BASE 0x2400
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#define MVGBE_PORTR_SIZE 0x400
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#define MVGBE_PXC 0x000 /* Port Configuration */
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#define MVGBE_PXCX 0x004 /* Port Configuration Extend */
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#define MVGBE_MIISP 0x008 /* MII Serial Parameters */
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#define MVGBE_GMIISP 0x00c /* GMII Serial Params */
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#define MVGBE_EVLANE 0x010 /* VLAN EtherType */
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#define MVGBE_MACAL 0x014 /* MAC Address Low */
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#define MVGBE_MACAH 0x018 /* MAC Address High */
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#define MVGBE_SDC 0x01c /* SDMA Configuration */
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#define MVGBE_DSCP(n) (0x020 + ((n) << 2))
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#define MVGBE_PSC 0x03c /* Port Serial Control0 */
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#define MVGBE_VPT2P 0x040 /* VLAN Priority Tag to Priority */
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#define MVGBE_PS 0x044 /* Ethernet Port Status */
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#define MVGBE_TQC 0x048 /* Transmit Queue Command */
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#define MVGBE_PSC1 0x04c /* Port Serial Control1 */
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#define MVGBE_MH 0x054 /* Marvell Header */
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#define MVGBE_MTU 0x058 /* Max Transmit Unit */
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#define MVGBE_IC 0x060 /* Port Interrupt Cause */
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#define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */
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#define MVGBE_PIM 0x068 /* Port Interrupt Mask */
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#define MVGBE_PEIM 0x06c /* Port Extend Interrupt Mask */
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#define MVGBE_PRFUT 0x070 /* Port Rx FIFO Urgent Threshold */
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#define MVGBE_PTFUT 0x074 /* Port Tx FIFO Urgent Threshold */
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#define MVGBE_PXTFTT 0x078 /* Port Tx FIFO Threshold */
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#define MVGBE_PMFS 0x07c /* Port Rx Minimal Frame Size */
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#define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */
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#define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */
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#define MVGBE_PIAE 0x094 /* Port Internal Address Error */
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#define MVGBE_AIP0ADR 0x098 /* Arp IP0 Address */
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#define MVGBE_AIP1ADR 0x09c /* Arp IP1 Address */
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#define MVGBE_SERDESCFG 0x0a0 /* Serdes Configuration */
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#define MVGBE_SERDESSTS 0x0a4 /* Serdes Status */
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#define MVGBE_ETP 0x0bc /* Ethernet Type Priority */
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#define MVGBE_TQFPC 0x0dc /* Transmit Queue Fixed Priority Cfg */
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#define MVGBE_OMSCD 0x0f4 /* One mS Clock Divider */
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#define MVGBE_PFCCD 0x0f8 /* Periodic Flow Control Clock Divider*/
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#define MVGBE_PACC 0x100 /* Port Acceleration Mode */
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#define MVGBE_PBMADDR 0x104 /* Port BM Address */
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#define MVGBE_PV 0x1bc /* Port Version */
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#define MVGBE_CRDP(n) (0x20c + ((n) << 4))
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/* Ethernet Current Receive Descriptor Pointers */
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#define MVGBE_RQC 0x280 /* Receive Queue Command */
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#define MVGBE_TCSDP 0x284 /* Tx Current Served Desc Pointer */
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#define MVGBE_TCQDP 0x2c0 /* Tx Current Queue Desc Pointer */
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#define MVGBE_TQTBCOUNT(q) (0x300 + ((q) << 4))
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/* Transmit Queue Token-Bucket Counter */
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#define MVGBE_TQTBCONFIG(q) (0x304 + ((q) << 4))
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/* Transmit Queue Token-Bucket Configuration */
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#define MVGBE_TQAC(q) (0x308 + ((q) << 4))
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/* Transmit Queue Arbiter Configuration */
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#define MVGBE_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) /* Port CPUn to Queue */
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#define MVGBE_PRXITTH(q) (0x2540 + ((q) << 2) /* Port RX Intr Threshold*/
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#define MVGBE_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/
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#define MVGBE_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */
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#define MVGBE_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */
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#define MVGBE_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */
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#define MVGBE_PMIC 0x25b0 /* Port Misc Interrupt Cause */
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#define MVGBE_PMIM 0x25b4 /* Port Misc Interrupt Mask */
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#define MVGBE_PIE 0x25b8 /* Port Interrupt Enable */
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#define MVGBE_PMACC0 0x2c00 /* Port MAC Control 0 */
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#define MVGBE_PMACC1 0x2c04 /* Port MAC Control 1 */
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#define MVGBE_PMACC2 0x2c08 /* Port MAC Control 2 */
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#define MVGBE_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
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#define MVGBE_PS0 0x2c10 /* Port Status 0 */
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#define MVGBE_PSPC 0x2c14 /* Port Serial Parameters Config */
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#define MVGBE_PIC_2 0x2c20 /* Port Interrupt Cause */
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#define MVGBE_PIM_2 0x2c24 /* Port Interrupt Mask */
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#define MVGBE_PPRBSS 0x2c38 /* Port PRBS Status */
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#define MVGBE_PPRBSEC 0x2c3c /* Port PRBS Error Counter */
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#define MVGBE_PMACC3 0x2c48 /* Port MAC Control 3 */
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#define MVGBE_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/
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#define MVGBE_PMACC4 0x2c90 /* Port MAC Control 4 */
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#define MVGBE_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */
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#define MVGBE_LPIC0 0x2cc0 /* LowPowerIdle control 0 */
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#define MVGBE_LPIC1 0x2cc4 /* LPI control 1 */
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#define MVGBE_LPIC2 0x2cc8 /* LPI control 2 */
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#define MVGBE_LPIS 0x2ccc /* LPI status */
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#define MVGBE_LPIC 0x2cd0 /* LPI counter */
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#define MVGBE_PPLLC 0x2e04 /* Power and PLL Control */
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#define MVGBE_DLE 0x2e8c /* Digital Loopback Enable */
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#define MVGBE_RCS 0x2f18 /* Reference Clock Select */
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/* MAC MIB Counters 0x3000 - 0x307c */
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/* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
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#define MVGBE_PORTDAFR_BASE 0x3400
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#define MVGBE_PORTDAFR_SIZE 0x400
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#define MVGBE_NDFSMT 0x40
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#define MVGBE_DFSMT 0x000
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/* Destination Address Filter Special Multicast Table */
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#define MVGBE_NDFOMT 0x40
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#define MVGBE_DFOMT 0x100
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/* Destination Address Filter Other Multicast Table */
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#define MVGBE_NDFUT 0x4
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#define MVGBE_DFUT 0x200
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/* Destination Address Filter Unicast Table */
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#define MVGBE_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/
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#define MVGBE_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/
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#define MVGBE_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/
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#define MVGBE_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/
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#define MVGBE_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/
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#define MVGBE_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
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#define MVGBE_PTXINIT 0x3cf0 /* Port TX Initialization */
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#define MVGBE_PTXDOSD 0x3cf4 /* Port TX Disable Outstanding Reads */
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#define MVGBE_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/
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#define MVGBE_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */
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#define MVGBE_TXNB 0x3cfc /* Tx Number of New Bytes */
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#define MVGBE_TXGB 0x3d00 /* Tx Green Number of Bytes */
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#define MVGBE_TXYB 0x3d04 /* Tx Yellow Number of Bytes */
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/* Tx DMA Packet Modification Registers 0x3d00 - 0x3dff */
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/* Tx DMA Queue Arbiter Registers 0x3e00 - 0x3eff */
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/* PHY Address (MVGBE_PHYADDR) */
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#define MVGBE_PHYADDR_PHYAD_MASK 0x1f
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#define MVGBE_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5))
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/* SMI register fields (MVGBE_SMI) */
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#define MVGBE_SMI_DATA_MASK 0x0000ffff
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#define MVGBE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16)
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#define MVGBE_SMI_REGAD(reg) (((reg) & 0x1f) << 21)
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#define MVGBE_SMI_OPCODE_WRITE (0 << 26)
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#define MVGBE_SMI_OPCODE_READ (1 << 26)
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#define MVGBE_SMI_READVALID (1 << 27)
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#define MVGBE_SMI_BUSY (1 << 28)
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/* Ethernet Unit Default ID (MVGBE_EUDID) */
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#define MVGBE_EUDID_DIDR_MASK 0x0000000f
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#define MVGBE_EUDID_DATTR_MASK 0x00000ff0
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/* Ethernet Unit Reserved (MVGBE_EU) */
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#define MVGBE_EU_FASTMDC (1 << 0)
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#define MVGBE_EU_ACCS (1 << 1)
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/* Ethernet Unit Interrupt Cause (MVGBE_EUIC) */
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#define MVGBE_EUIC_ETHERINTSUM (1 << 0)
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#define MVGBE_EUIC_PARITY (1 << 1)
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#define MVGBE_EUIC_ADDRVIOL (1 << 2)
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#define MVGBE_EUIC_ADDRVNOMATCH (1 << 3)
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#define MVGBE_EUIC_SMIDONE (1 << 4)
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#define MVGBE_EUIC_COUNTWA (1 << 5)
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#define MVGBE_EUIC_INTADDRERR (1 << 7)
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#define MVGBE_EUIC_PORT0DPERR (1 << 9)
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#define MVGBE_EUIC_TOPDPERR (1 << 12)
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/* Ethernet Unit Internal Addr Error (MVGBE_EUIAE) */
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#define MVGBE_EUIAE_INTADDR_MASK 0x000001ff
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/* Ethernet Unit Port Pads Calibration (MVGBE_EUPCR) */
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#define MVGBE_EUPCR_DRVN_MASK 0x0000001f
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#define MVGBE_EUPCR_TUNEEN (1 << 16)
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#define MVGBE_EUPCR_LOCKN_MASK 0x003e0000
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#define MVGBE_EUPCR_OFFSET_MASK 0x1f000000 /* Reserved */
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#define MVGBE_EUPCR_WREN (1 << 31)
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/* Ethernet Unit Control (MVGBE_EUC) */
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#define MVGBE_EUC_PORT0DPPAR (1 << 0)
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#define MVGBE_EUC_POLLING (1 << 1)
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#define MVGBE_EUC_TOPDPPAR (1 << 3)
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#define MVGBE_EUC_PORT0PW (1 << 16)
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#define MVGBE_EUC_PORTRESET (1 << 24)
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#define MVGBE_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25)
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/* Base Address (MVGBE_BASEADDR) */
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#define MVGBE_BASEADDR_TARGET(target) ((target) & 0xf)
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#define MVGBE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8)
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#define MVGBE_BASEADDR_BASE(base) ((base) & 0xffff0000)
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/* Size (MVGBE_S) */
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#define MVGBE_S_SIZE(size) (((size) - 1) & 0xffff0000)
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/* Base Address Enable (MVGBE_BARE) */
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#define MVGBE_BARE_EN_MASK ((1 << MVGBE_NWINDOW) - 1)
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#define MVGBE_BARE_EN(win) ((1 << (win)) & MVGBE_BARE_EN_MASK)
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/* Ethernet Port Access Protect (MVGBE_EPAP) */
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#define MVGBE_EPAP_AC_NAC 0x0 /* No access allowed */
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#define MVGBE_EPAP_AC_RO 0x1 /* Read Only */
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#define MVGBE_EPAP_AC_FA 0x3 /* Full access (r/w) */
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#define MVGBE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2))
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/* Port Configuration (MVGBE_PXC) */
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#define MVGBE_PXC_UPM (1 << 0) /* Uni Promisc mode */
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#define MVGBE_PXC_RXQ(q) ((q) << 1)
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#define MVGBE_PXC_RXQ_MASK MVGBE_PXC_RXQ(7)
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#define MVGBE_PXC_RXQARP(q) ((q) << 4)
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#define MVGBE_PXC_RXQARP_MASK MVGBE_PXC_RXQARP(7)
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#define MVGBE_PXC_RB (1 << 7) /* Rej mode of MAC */
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#define MVGBE_PXC_RBIP (1 << 8)
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#define MVGBE_PXC_RBARP (1 << 9)
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#define MVGBE_PXC_AMNOTXES (1 << 12)
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#define MVGBE_PXC_RBARPF (1 << 13)
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#define MVGBE_PXC_TCPCAPEN (1 << 14)
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#define MVGBE_PXC_UDPCAPEN (1 << 15)
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#define MVGBE_PXC_TCPQ(q) ((q) << 16)
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#define MVGBE_PXC_TCPQ_MASK MVGBE_PXC_TCPQ(7)
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#define MVGBE_PXC_UDPQ(q) ((q) << 19)
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#define MVGBE_PXC_UDPQ_MASK MVGBE_PXC_UDPQ(7)
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#define MVGBE_PXC_BPDUQ(q) ((q) << 22)
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#define MVGBE_PXC_BPDUQ_MASK MVGBE_PXC_BPDUQ(7)
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#define MVGBE_PXC_RXCS (1 << 25)
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/* Port Configuration Extend (MVGBE_PXCX) */
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#define MVGBE_PXCX_SPAN (1 << 1)
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#define MVGBE_PXCX_TXCRCDIS (1 << 3)
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/* MII Serial Parameters (MVGBE_MIISP) */
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#define MVGBE_MIISP_JAMLENGTH_12KBIT 0x00000000
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#define MVGBE_MIISP_JAMLENGTH_24KBIT 0x00000001
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#define MVGBE_MIISP_JAMLENGTH_32KBIT 0x00000002
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#define MVGBE_MIISP_JAMLENGTH_48KBIT 0x00000003
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#define MVGBE_MIISP_JAMIPG(x) (((x) & 0x7c) << 0)
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#define MVGBE_MIISP_IPGJAMTODATA(x) (((x) & 0x7c) << 5)
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#define MVGBE_MIISP_IPGDATA(x) (((x) & 0x7c) << 10)
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#define MVGBE_MIISP_DATABLIND(x) (((x) & 0x1f) << 17)
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|
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/* GMII Serial Parameters (MVGBE_GMIISP) */
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#define MVGBE_GMIISP_IPGDATA(x) (((x) >> 4) & 0x7)
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|
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/* SDMA Configuration (MVGBE_SDC) */
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#define MVGBE_SDC_RIFB (1 << 0)
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#define MVGBE_SDC_RXBSZ(x) ((x) << 1)
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#define MVGBE_SDC_RXBSZ_MASK MVGBE_SDC_RXBSZ(7)
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#define MVGBE_SDC_RXBSZ_1_64BITWORDS MVGBE_SDC_RXBSZ(0)
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#define MVGBE_SDC_RXBSZ_2_64BITWORDS MVGBE_SDC_RXBSZ(1)
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#define MVGBE_SDC_RXBSZ_4_64BITWORDS MVGBE_SDC_RXBSZ(2)
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#define MVGBE_SDC_RXBSZ_8_64BITWORDS MVGBE_SDC_RXBSZ(3)
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#define MVGBE_SDC_RXBSZ_16_64BITWORDS MVGBE_SDC_RXBSZ(4)
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#define MVGBE_SDC_BLMR (1 << 4)
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#define MVGBE_SDC_BLMT (1 << 5)
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#define MVGBE_SDC_SWAPMODE (1 << 6)
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#define MVGBE_SDC_IPGINTRX_V1_MASK __BITS(21, 8)
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#define MVGBE_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7))
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#define MVGBE_SDC_IPGINTRX_V1(x) (((x) << 4) \
|
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& MVGBE_SDC_IPGINTRX_V1_MASK)
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#define MVGBE_SDC_IPGINTRX_V2(x) ((((x) & 0x8000) << 10) \
|
|
| (((x) & 0x7fff) << 7))
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#define MVGBE_SDC_IPGINTRX_V1_MAX 0x3fff
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#define MVGBE_SDC_IPGINTRX_V2_MAX 0xffff
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#define MVGBE_SDC_TXBSZ(x) ((x) << 22)
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#define MVGBE_SDC_TXBSZ_MASK MVGBE_SDC_TXBSZ(7)
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#define MVGBE_SDC_TXBSZ_1_64BITWORDS MVGBE_SDC_TXBSZ(0)
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#define MVGBE_SDC_TXBSZ_2_64BITWORDS MVGBE_SDC_TXBSZ(1)
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#define MVGBE_SDC_TXBSZ_4_64BITWORDS MVGBE_SDC_TXBSZ(2)
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#define MVGBE_SDC_TXBSZ_8_64BITWORDS MVGBE_SDC_TXBSZ(3)
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#define MVGBE_SDC_TXBSZ_16_64BITWORDS MVGBE_SDC_TXBSZ(4)
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/* Port Serial Control (MVGBE_PSC) */
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#define MVGBE_PSC_PORTEN (1 << 0)
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#define MVGBE_PSC_FLP (1 << 1) /* Force_Link_Pass */
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#define MVGBE_PSC_ANDUPLEX (1 << 2) /* auto nego */
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#define MVGBE_PSC_ANFC (1 << 3)
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#define MVGBE_PSC_PAUSEADV (1 << 4)
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#define MVGBE_PSC_FFCMODE (1 << 5) /* Force FC */
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#define MVGBE_PSC_FBPMODE (1 << 7) /* Back pressure */
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#define MVGBE_PSC_RESERVED (1 << 9) /* Must be set to 1 */
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#define MVGBE_PSC_FLFAIL (1 << 10) /* Force Link Fail */
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#define MVGBE_PSC_ANSPEED (1 << 13)
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#define MVGBE_PSC_DTEADVERT (1 << 14)
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#define MVGBE_PSC_MRU(x) ((x) << 17)
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#define MVGBE_PSC_MRU_MASK MVGBE_PSC_MRU(7)
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#define MVGBE_PSC_MRU_1518 0
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#define MVGBE_PSC_MRU_1522 1
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#define MVGBE_PSC_MRU_1552 2
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#define MVGBE_PSC_MRU_9022 3
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#define MVGBE_PSC_MRU_9192 4
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#define MVGBE_PSC_MRU_9700 5
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#define MVGBE_PSC_SETFULLDX (1 << 21)
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#define MVGBE_PSC_SETFCEN (1 << 22)
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#define MVGBE_PSC_SETGMIISPEED (1 << 23)
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#define MVGBE_PSC_SETMIISPEED (1 << 24)
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|
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/* Ethernet Port Status (MVGBE_PS) */
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#define MVGBE_PS_LINKUP (1 << 1)
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#define MVGBE_PS_FULLDX (1 << 2)
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#define MVGBE_PS_ENFC (1 << 3)
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#define MVGBE_PS_GMIISPEED (1 << 4)
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#define MVGBE_PS_MIISPEED (1 << 5)
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#define MVGBE_PS_TXINPROG (1 << 7)
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#define MVGBE_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */
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|
#define MVGBE_PS_RXFIFOEMPTY (1 << 16)
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|
/* Armada XP */
|
|
#define MVGBE_PS_TXINPROG_MASK (0xff << 0)
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|
#define MVGBE_PS_TXINPROG_(q) (1 << ((q) + 0))
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#define MVGBE_PS_TXFIFOEMP_MASK (0xff << 8)
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|
#define MVGBE_PS_TXFIFOEMP_(q) (1 << ((q) + 8))
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|
|
|
/* Transmit Queue Command (MVGBE_TQC) */
|
|
#define MVGBE_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */
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#define MVGBE_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */
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|
|
|
/* Port Serial Control 1 (MVGBE_PSC1) */
|
|
#define MVGBE_PSC1_PCSLB (1 << 1)
|
|
#define MVGBE_PSC1_RGMIIEN (1 << 3) /* RGMII */
|
|
#define MVGBE_PSC1_PRST (1 << 4) /* Port Reset */
|
|
|
|
/* Port Interrupt Cause (MVGBE_IC) */
|
|
#define MVGBE_IC_RXBUF (1 << 0)
|
|
#define MVGBE_IC_EXTEND (1 << 1)
|
|
#define MVGBE_IC_RXBUFQ_MASK (0xff << 2)
|
|
#define MVGBE_IC_RXBUFQ(q) (1 << ((q) + 2))
|
|
#define MVGBE_IC_RXERROR (1 << 10)
|
|
#define MVGBE_IC_RXERRQ_MASK (0xff << 11)
|
|
#define MVGBE_IC_RXERRQ(q) (1 << ((q) + 11))
|
|
#define MVGBE_IC_TXEND(q) (1 << ((q) + 19))
|
|
#define MVGBE_IC_ETHERINTSUM (1 << 31)
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|
|
|
/* Port Interrupt Cause Extend (MVGBE_ICE) */
|
|
#define MVGBE_ICE_TXBUF_MASK (0xff << + 0)
|
|
#define MVGBE_ICE_TXBUF(q) (1 << ((q) + 0))
|
|
#define MVGBE_ICE_TXERR_MASK (0xff << + 8)
|
|
#define MVGBE_ICE_TXERR(q) (1 << ((q) + 8))
|
|
#define MVGBE_ICE_PHYSTC (1 << 16)
|
|
#define MVGBE_ICE_PTP (1 << 17)
|
|
#define MVGBE_ICE_RXOVR (1 << 18)
|
|
#define MVGBE_ICE_TXUDR (1 << 19)
|
|
#define MVGBE_ICE_LINKCHG (1 << 20)
|
|
#define MVGBE_ICE_SERDESREALIGN (1 << 21)
|
|
#define MVGBE_ICE_INTADDRERR (1 << 23)
|
|
#define MVGBE_ICE_SYNCCHANGED (1 << 24)
|
|
#define MVGBE_ICE_PRBSERROR (1 << 25)
|
|
#define MVGBE_ICE_ETHERINTSUM (1 << 31)
|
|
|
|
/* Port Tx FIFO Urgent Threshold (MVGBE_PTFUT) */
|
|
#define MVGBE_PTFUT_IPGINTTX_V1_MASK __BITS(17, 4)
|
|
#define MVGBE_PTFUT_IPGINTTX_V2_MASK __BITS(19, 4)
|
|
#define MVGBE_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V1_MASK)
|
|
#define MVGBE_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V2_MASK)
|
|
#define MVGBE_PTFUT_IPGINTTX_V1_MAX 0x3fff
|
|
#define MVGBE_PTFUT_IPGINTTX_V2_MAX 0xffff
|
|
|
|
/* Port Rx Minimal Frame Size (MVGBE_PMFS) */
|
|
#define MVGBE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
|
|
/* RxMFS = 40,44,48,52,56,60,64 bytes */
|
|
|
|
/* Transmit Queue Fixed Priority Configuration */
|
|
#define MVGBE_TQFPC_EN(q) (1 << (q))
|
|
|
|
/* Receive Queue Command (MVGBE_RQC) */
|
|
#define MVGBE_RQC_ENQ_MASK (0xff << 0) /* Enable Q */
|
|
#define MVGBE_RQC_ENQ(n) (1 << (0 + (n)))
|
|
#define MVGBE_RQC_DISQ_MASK (0xff << 8) /* Disable Q */
|
|
#define MVGBE_RQC_DISQ(n) (1 << (8 + (n)))
|
|
#define MVGBE_RQC_DISQ_DISABLE(q) ((q) << 8)
|
|
|
|
/* Destination Address Filter Registers (MVGBE_DF{SM,OM,U}T) */
|
|
#define MVGBE_DF(n, x) ((x) << (8 * (n)))
|
|
#define MVGBE_DF_PASS (1 << 0)
|
|
#define MVGBE_DF_QUEUE(q) ((q) << 1)
|
|
#define MVGBE_DF_QUEUE_MASK ((7) << 1)
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|
|
|
|
|
/* Port Acceleration Mode (MVGBE_PACC) */
|
|
#define MVGVE_PACC_ACCELERATIONMODE_MASK 0x7
|
|
#define MVGVE_PACC_ACCELERATIONMODE_BM 0x0 /* Basic Mode */
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|
#define MVGVE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */
|
|
#define MVGVE_PACC_ACCELERATIONMODE_EDMBM 0x2 /* with BM */
|
|
#define MVGVE_PACC_ACCELERATIONMODE_EDMPNC 0x3 /* with PnC */
|
|
#define MVGVE_PACC_ACCELERATIONMODE_EDMBPMNC 0x4 /* with BM & PnC */
|
|
|
|
/* Port BM Address (MVGBE_PBMADDR) */
|
|
#define MVGBE_PBMADDR_BMADDRESS_MASK 0xfffff800
|
|
|
|
/* Ether Type Priority (MVGBE_ETP) */
|
|
#define MVGBE_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */
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|
#define MVGBE_ETP_ETHERTYPEPRIFRSTEN (1 << 1)
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|
#define MVGBE_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
|
|
#define MVGBE_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/
|
|
#define MVGBE_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */
|
|
|
|
/* RX Hardware Forwarding (0_1, 2_3,..., 8_9) (MVGBE_RXHWFWD) */
|
|
#define MVGBE_RXHWFWD_PORT_BASEADDRESS(p, x) xxxxx
|
|
|
|
/* RX Hardware Forwarding Pointer (MVGBE_RXHWFWDPTR) */
|
|
#define MVGBE_RXHWFWDPTR_QUEUENO(q) ((q) << 8) /* Queue Number */
|
|
#define MVGBE_RXHWFWDPTR_PORTNO(p) ((p) << 11) /* Port Number */
|
|
|
|
/* RX Hardware Forwarding Threshold (MVGBE_RXHWFWDTH) */
|
|
#define MVGBE_RXHWFWDTH_DROPRNDGENBITS(n) (((n) & 0x3ff) << 0)
|
|
#define MVGBE_RXHWFWDTH_DROPTHRESHOLD(n) (((n) & 0xf) << 16)
|
|
|
|
/* RX Control (MVGBE_RXCTRL) */
|
|
#define MVGBE_RXCTRL_PACKETCOLORSRCSELECT(x) (1 << 0)
|
|
#define MVGBE_RXCTRL_GEMPORTIDSRCSEL(x) ((x) << 4)
|
|
#define MVGBE_RXCTRL_TXHWFRWMQSRC(x) (1 << 8)
|
|
#define MVGBE_RXCTRL_RX_MH_SELECT(x) ((x) << 12)
|
|
#define MVGBE_RXCTRL_RX_TX_SRC_SELECT (1 << 16)
|
|
#define MVGBE_RXCTRL_HWFRWDENB (1 << 17)
|
|
#define MVGBE_RXCTRL_HWFRWDSHORTPOOLID(id) (((id) & 0x3) << 20)
|
|
#define MVGBE_RXCTRL_HWFRWDLONGPOOLID(id) (((id) & 0x3) << 22)
|
|
|
|
/* Port RX queues Configuration (MVGBE_PRXC) */
|
|
#define MVGBE_PRXC_POOLIDSHORT(i) (((i) & 0x3) << 4)
|
|
#define MVGBE_PRXC_POOLIDLONG(i) (((i) & 0x3) << 6)
|
|
#define MVGBE_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8)
|
|
#define MVGBE_PRXC_USERPREFETCHCMND0 (1 << 16)
|
|
|
|
/* Port RX queues Snoop (MVGBE_PRXSNP) */
|
|
#define MVGBE_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0)
|
|
#define MVGBE_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16)
|
|
|
|
/* Port RX queues Snoop (MVGBE_PRXSNP) */
|
|
#define MVGBE_PRXF01_PREFETCHCOMMAND0(c) (((c) & 0xffff) << 0) xxxx
|
|
#define MVGBE_PRXF01_PREFETCHCOMMAND1(c) (((c) & 0xffff) << 16) xxxx
|
|
|
|
/* Port RX queues Descriptors Queue Size (MVGBE_PRXDQS) */
|
|
#define MVGBE_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x0003fff) << 0)
|
|
#define MVGBE_PRXDQS_BUFFERSIZE(s) (((s) & 0xfff80000) << 19)
|
|
|
|
/* Port RX queues Descriptors Queue Threshold (MVGBE_PRXDQTH) */
|
|
/* Occupied Descriptors Threshold */
|
|
#define MVGBE_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0)
|
|
/* Non Occupied Descriptors Threshold */
|
|
#define MVGBE_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16)
|
|
|
|
/* Port RX queues Status (MVGBE_PRXS) */
|
|
/* Occupied Descriptors Counter */
|
|
#define MVGBE_PRXS_ODC(x) (((x) & 0x3fff) << 0)
|
|
/* Non Occupied Descriptors Counter */
|
|
#define MVGBE_PRXS_NODC(x) (((x) & 0x3fff) << 16)
|
|
|
|
/* Port RX queues Status Update (MVGBE_PRXSU) */
|
|
#define MVGBE_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0)
|
|
#define MVGBE_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16)
|
|
|
|
/* Port RX Flow Control (MVGBE_PRXFC) */
|
|
#define MVGBE_PRXFC_PERPRIOFCGENCONTROL (1 << 0)
|
|
#define MVGBE_PRXFC_TXPAUSECONTROL (1 << 1)
|
|
|
|
/* Port RX_TX Pause (MVGBE_PRXTXP) */
|
|
#define MVGBE_PRXTXP_TXPAUSE(x) ((x) & 0xff)
|
|
|
|
/* Port RX Flow Control Generation (MVGBE_PRXFCG) */
|
|
#define MVGBE_PRXFCG_PERPRIOFCGENDATA (1 << 0)
|
|
#define MVGBE_PRXFCG_PERPRIOFCGENQNO(x) (((x) & 0x7) << 4)
|
|
|
|
/* Port RX Initialization (MVGBE_PRXINIT) */
|
|
#define MVGBE_PRXINIT_RXDMAINIT (1 << 0)
|
|
|
|
/* TX Number of New Bytes (MVGBE_TXNB) */
|
|
#define MVGBE_TXNB_NOOFNEWBYTES(b) (((b) & 0xffff) << 0)
|
|
#define MVGBE_TXNB_PKTQNO(q) (((q) & 0x7) << 28)
|
|
#define MVGBE_TXNB_PKTCOLOR (1 << 31)
|
|
|
|
/* Port TX queues Descriptors Queue Size (MVGBE_PTXDQS) */
|
|
/* Descriptors Queue Size */
|
|
#define MVGBE_PTXDQS_DQS(x) (((x) & 0x3fff) << 0)
|
|
/* Transmitted Buffer Threshold */
|
|
#define MVGBE_PTXDQS_TBT(x) (((x) & 0x3fff) << 16)
|
|
|
|
/* Port TX queues Status (MVGBE_PTXS) */
|
|
/* Pending Descriptors Counter */
|
|
#define MVGBE_PTXDQS_PDC(x) (((x) & 0x3fff) << 0)
|
|
/* Transmitted Buffer Counter */
|
|
#define MVGBE_PTXS_TBC(x) (((x) & 0x3fff) << 16)
|
|
|
|
/* Port TX queues Status Update (MVGBE_PTXSU) */
|
|
/* Number Of Written Descriptors */
|
|
#define MVGBE_PTXSU_NOWD(x) (((x) & 0xff) << 0)
|
|
/* Number Of Released Buffers */
|
|
#define MVGBE_PTXSU_NORB(x) (((x) & 0xff) << 16)
|
|
|
|
/* TX Transmitted Buffers Counter (MVGBE_TXTBC) */
|
|
/* Transmitted Buffers Counter */
|
|
#define MVGBE_TXTBC_TBC(x) (((x) & 0x3fff) << 16)
|
|
|
|
/* Port TX Initialization (MVGBE_PTXINIT) */
|
|
#define MVGBE_PTXINIT_TXDMAINIT (1 << 0)
|
|
|
|
/* Marvell Header (MVGBE_MH) */
|
|
#define MVGBE_MH_MHEN (1 << 0)
|
|
#define MVGBE_MH_DAPREFIX (0x3 << 1)
|
|
#define MVGBE_MH_SPID (0xf << 4)
|
|
#define MVGBE_MH_MHMASK (0x3 << 8)
|
|
#define MVGBE_MH_MHMASK_8QUEUES (0x0 << 8)
|
|
#define MVGBE_MH_MHMASK_4QUEUES (0x1 << 8)
|
|
#define MVGBE_MH_MHMASK_2QUEUES (0x3 << 8)
|
|
#define MVGBE_MH_DSAEN_MASK (0x3 << 10)
|
|
#define MVGBE_MH_DSAEN_DISABLE (0x0 << 10)
|
|
#define MVGBE_MH_DSAEN_NONEXTENDED (0x1 << 10)
|
|
#define MVGBE_MH_DSAEN_EXTENDED (0x2 << 10)
|
|
|
|
/* Port Auto-Negotiation Configuration (MVGBE_PANC) */
|
|
#define MVGBE_PANC_FORCELINKFAIL (1 << 0)
|
|
#define MVGBE_PANC_FORCELINKPASS (1 << 1)
|
|
#define MVGBE_PANC_INBANDANEN (1 << 2)
|
|
#define MVGBE_PANC_INBANDANBYPASSEN (1 << 3)
|
|
#define MVGBE_PANC_INBANDRESTARTAN (1 << 4)
|
|
#define MVGBE_PANC_SETMIISPEED (1 << 5)
|
|
#define MVGBE_PANC_SETGMIISPEED (1 << 6)
|
|
#define MVGBE_PANC_ANSPEEDEN (1 << 7)
|
|
#define MVGBE_PANC_SETFCEN (1 << 8)
|
|
#define MVGBE_PANC_PAUSEADV (1 << 9)
|
|
#define MVGBE_PANC_ANFCEN (1 << 11)
|
|
#define MVGBE_PANC_SETFULLDX (1 << 12)
|
|
#define MVGBE_PANC_ANDUPLEXEN (1 << 13)
|
|
#define MVGBE_PANC_RESERVED (1 << 15)
|
|
|
|
/* Port MAC Control 0 (MVGBE_PMACC0) */
|
|
#define MVGBE_PMACC0_PORTEN (1 << 0)
|
|
#define MVGBE_PMACC0_PORTTYPE (1 << 1)
|
|
#define MVGBE_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x7ffc) << 2)
|
|
#define MVGBE_PMACC0_RESERVED (1 << 15)
|
|
|
|
/* Port MAC Control 1 (MVGBE_PMACC1) */
|
|
#define MVGBE_PMACC1_PCSLB (1 << 6)
|
|
|
|
/* Port MAC Control 2 (MVGBE_PMACC2) */
|
|
#define MVGBE_PMACC2_PCSEN (1 << 3)
|
|
#define MVGBE_PMACC2_RGMIIEN (1 << 4)
|
|
#define MVGBE_PMACC2_PADDINGDIS (1 << 5)
|
|
#define MVGBE_PMACC2_PORTMACRESET (1 << 6)
|
|
#define MVGBE_PMACC2_PRBSCHECKEN (1 << 10)
|
|
#define MVGBE_PMACC2_PRBSGENEN (1 << 11)
|
|
#define MVGBE_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */
|
|
#define MVGBE_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */
|
|
#define MVGBE_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */
|
|
#define MVGBE_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */
|
|
#define MVGBE_PMACC2_SDTT_OC (3 << 12) /* One Constant */
|
|
#define MVGBE_PMACC2_RESERVED (3 << 14)
|
|
|
|
/* Port MAC Control 3 (MVGBE_PMACC3) */
|
|
#define MVGBE_PMACC3_IPG_MASK 0x7f80
|
|
|
|
/* Port Interrupt Cause/Mask (MVGBE_PIC_2/MVGBE_PIM_2) */
|
|
#define MVGBE_PI_2_INTSUM (1 << 0)
|
|
#define MVGBE_PI_2_LSC (1 << 1) /* LinkStatus Change */
|
|
#define MVGBE_PI_2_ACOP (1 << 2) /* AnCompleted OnPort */
|
|
#define MVGBE_PI_2_AOOR (1 << 5) /* AddressOut Of Range */
|
|
#define MVGBE_PI_2_SSC (1 << 6) /* SyncStatus Change */
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#define MVGBE_PI_2_PRBSEOP (1 << 7) /* QSGMII PRBS error */
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#define MVGBE_PI_2_MIBCWA (1 << 15) /* MIB counter wrap around */
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#define MVGBE_PI_2_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */
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#define MVGBE_PI_2_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
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#define MVGBE_PI_2_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/
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#define MVGBE_PI_2_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
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#define MVGBE_PI_2_MIBCCD (1 << 14) /* MIB counters copy done */
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/* LPI Control 0 (MVGBE_LPIC0) */
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#define MVGBE_LPIC0_LILIMIT(x) (((x) & 0xff) << 0)
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#define MVGBE_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8)
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/* LPI Control 1 (MVGBE_LPIC1) */
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#define MVGBE_LPIC1_LPIRE (1 << 0) /* LPI request enable */
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#define MVGBE_LPIC1_LPIRF (1 << 1) /* LPI request force */
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#define MVGBE_LPIC1_LPIMM (1 << 2) /* LPI manual mode */
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#define MVGBE_LPIC1_TWLIMIT (((x) & 0xfff) << 4)
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/* LPI Status (MVGBE_LPIS) */
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#define MVGBE_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
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#define MVGBE_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */
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#define MVGBE_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */
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#define MVGBE_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */
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#define MVGBE_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */
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/* Port PRBS Status (MVGBE_PPRBSS) */
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#define MVGBE_PPRBSS_PRBSCHECKLOCKED (1 << 0)
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#define MVGBE_PPRBSS_PRBSCHECKRDY (1 << 1)
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/* Port Status 0 (MVGBE_PS0) */
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#define MVGBE_PS0_LINKUP (1 << 0)
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#define MVGBE_PS0_GMIISPEED (1 << 1)
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#define MVGBE_PS0_MIISPEED (1 << 2)
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#define MVGBE_PS0_FULLDX (1 << 3)
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#define MVGBE_PS0_RXFCEN (1 << 4)
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#define MVGBE_PS0_TXFCEN (1 << 5)
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#define MVGBE_PS0_PRP (1 << 6) /* Port Rx Pause */
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#define MVGBE_PS0_PTP (1 << 7) /* Port Tx Pause */
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#define MVGBE_PS0_PDP (1 << 8) /*Port is Doing Back-Pressure*/
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#define MVGBE_PS0_SYNCFAIL10MS (1 << 10)
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#define MVGBE_PS0_ANDONE (1 << 11)
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#define MVGBE_PS0_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */
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#define MVGBE_PS0_SYNCOK (1 << 14)
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/* Port CPUn to Queue (MVGBE_PCP2Q) */
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#define MVGBE_PCP2Q_RXQAE(q) (1 << ((q) + << 0))/*QueueAccessEnable*/
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#define MVGBE_PCP2Q_TXQAE(q) (1 << ((q) + << 8))/*QueueAccessEnable*/
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/* Port RX_TX Threshold Interrupt Cause/Mask (MVGBE_PRXTXTIC/MVGBE_PRXTXTIM) */
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#define MVGBE_PRXTXTI_TBTCQ(q) (1 << ((q) + 0))
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#define MVGBE_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8))
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#define MVGBE_PRXTXTI_RDTAQ(q) (1 << ((q) + 16))
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#define MVGBE_PRXTXTI_PRXTXICSUMMARY (1 << 29)
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#define MVGBE_PRXTXTI_PTXERRORSUMMARY (1 << 30)
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#define MVGBE_PRXTXTI_PMISCICSUMMARY (1 << 31)
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/* Port RX_TX Interrupt Cause/Mask (MVGBE_PRXTXIC/MVGBE_PRXTXIM) */
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#define MVGBE_PRXTXI_TBRQ(q) (1 << ((q) + 0))
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#define MVGBE_PRXTXI_RPQ(q) (1 << ((q) + 8))
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#define MVGBE_PRXTXI_RREQ(q) (1 << ((q) + 16))
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#define MVGBE_PRXTXI_PRXTXTHICSUMMARY (1 << 29)
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#define MVGBE_PRXTXI_PTXERRORSUMMARY (1 << 30)
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#define MVGBE_PRXTXI_PMISCICSUMMARY (1 << 31)
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/* Port Misc Interrupt Cause/Mask (MVGBE_PMIC/MVGBE_PMIM) */
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#define MVGBE_PMI_PHYSTATUSCHNG (1 << 0)
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#define MVGBE_PMI_LINKCHANGE (1 << 1)
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#define MVGBE_PMI_PTP (1 << 4)
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#define MVGBE_PMI_PME (1 << 6) /* Packet Modification Error */
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#define MVGBE_PMI_IAE (1 << 7) /* Internal Address Error */
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#define MVGBE_PMI_RXOVERRUN (1 << 8)
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#define MVGBE_PMI_RXCRCERROR (1 << 9)
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#define MVGBE_PMI_RXLARGEPACKET (1 << 10)
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#define MVGBE_PMI_TXUNDRN (1 << 11)
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#define MVGBE_PMI_PRBSERROR (1 << 12)
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#define MVGBE_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */
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#define MVGBE_PMI_RNBTP(q) (1 << ((q) + 16)) /* RxNoBuffersToPool*/
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#define MVGBE_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */
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/* Port Interrupt Enable (MVGBE_PIE) */
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#define MVGBE_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0))
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#define MVGBE_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8))
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/* Power and PLL Control (MVGBE_PPLLC) */
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#define MVGBE_PPLLC_REF_FREF_SEL_MASK (0xf << 0)
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#define MVGBE_PPLLC_PHY_MODE_MASK (7 << 5)
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#define MVGBE_PPLLC_PHY_MODE_SATA (0 << 5)
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#define MVGBE_PPLLC_PHY_MODE_SAS (1 << 5)
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#define MVGBE_PPLLC_PLL_LOCK (1 << 8)
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#define MVGBE_PPLLC_PU_DFE (1 << 10)
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#define MVGBE_PPLLC_PU_TX_INTP (1 << 11)
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#define MVGBE_PPLLC_PU_TX (1 << 12)
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#define MVGBE_PPLLC_PU_RX (1 << 13)
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#define MVGBE_PPLLC_PU_PLL (1 << 14)
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/* Digital Loopback Enable (MVGBE_DLE) */
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#define MVGBE_DLE_LOCAL_SEL_BITS_MASK (3 << 10)
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#define MVGBE_DLE_LOCAL_SEL_BITS_10BITS (0 << 10)
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#define MVGBE_DLE_LOCAL_SEL_BITS_20BITS (1 << 10)
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#define MVGBE_DLE_LOCAL_SEL_BITS_40BITS (2 << 10)
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#define MVGBE_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12)
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#define MVGBE_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13)
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#define MVGBE_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14)
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#define MVGBE_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15)
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/* Reference Clock Select (MVGBE_RCS) */
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#define MVGBE_RCS_REFCLK_SEL (1 << 10)
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/*
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* Set the chip's packet size limit to 9022.
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* (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN)
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*/
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#define MVGBE_MRU 9022
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#define MVGBE_RXBUF_ALIGN 32 /* Cache line size */
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#define MVGBE_RXBUF_MASK (MVGBE_RXBUF_ALIGN - 1)
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#define MVGBE_HWHEADER_SIZE 2
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/*
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* DMA descriptors
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* Despite the documentation saying these descriptors only need to be
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* aligned to 16-byte boundaries, 32-byte alignment seems to be required
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* by the hardware. We'll just pad them out to that to make it easier.
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*/
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struct mvgbe_tx_desc {
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#ifdef MVGBE_BIG_ENDIAN
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uint16_t bytecnt; /* Descriptor buffer byte count */
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uint16_t l4ichk; /* CPU provided TCP Checksum */
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uint32_t cmdsts; /* Descriptor command status */
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uint32_t nextdescptr; /* Next descriptor pointer */
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uint32_t bufptr; /* Descriptor buffer pointer */
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#else
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uint32_t cmdsts; /* Descriptor command status */
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uint16_t l4ichk; /* CPU provided TCP Checksum */
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uint16_t bytecnt; /* Descriptor buffer byte count */
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uint32_t bufptr; /* Descriptor buffer pointer */
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uint32_t nextdescptr; /* Next descriptor pointer */
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#endif
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uint32_t _padding[4];
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} __packed;
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struct mvgbe_rx_desc {
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#ifdef MVGBE_BIG_ENDIAN
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uint16_t bytecnt; /* Descriptor buffer byte count */
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uint16_t bufsize; /* Buffer size */
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uint32_t cmdsts; /* Descriptor command status */
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uint32_t nextdescptr; /* Next descriptor pointer */
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uint32_t bufptr; /* Descriptor buffer pointer */
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#else
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uint32_t cmdsts; /* Descriptor command status */
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uint16_t bufsize; /* Buffer size */
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uint16_t bytecnt; /* Descriptor buffer byte count */
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uint32_t bufptr; /* Descriptor buffer pointer */
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uint32_t nextdescptr; /* Next descriptor pointer */
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#endif
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uint32_t _padding[4];
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} __packed;
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#define MVGBE_ERROR_SUMMARY (1 << 0)
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#define MVGBE_BUFFER_OWNED_MASK (1 << 31)
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#define MVGBE_BUFFER_OWNED_BY_HOST (0 << 31)
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#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
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#define MVGBE_TX_ERROR_CODE_MASK (3 << 1)
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#define MVGBE_TX_LATE_COLLISION_ERROR (0 << 1)
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#define MVGBE_TX_UNDERRUN_ERROR (1 << 1)
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#define MVGBE_TX_EXCESSIVE_COLLISION_ERRO (2 << 1)
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#define MVGBE_TX_LLC_SNAP_FORMAT (1 << 9)
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#define MVGBE_TX_IP_NO_FRAG (1 << 10)
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#define MVGBE_TX_IP_HEADER_LEN(len) ((len) << 11)
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#define MVGBE_TX_VLAN_TAGGED_FRAME (1 << 15)
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#define MVGBE_TX_L4_TYPE_TCP (0 << 16)
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#define MVGBE_TX_L4_TYPE_UDP (1 << 16)
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#define MVGBE_TX_GENERATE_L4_CHKSUM (1 << 17)
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#define MVGBE_TX_GENERATE_IP_CHKSUM (1 << 18)
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#define MVGBE_TX_ZERO_PADDING (1 << 19)
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#define MVGBE_TX_LAST_DESC (1 << 20)
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#define MVGBE_TX_FIRST_DESC (1 << 21)
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#define MVGBE_TX_GENERATE_CRC (1 << 22)
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#define MVGBE_TX_ENABLE_INTERRUPT (1 << 23)
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#define MVGBE_TX_AUTO_MODE (1 << 30)
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#define MVGBE_RX_ERROR_CODE_MASK (3 << 1)
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#define MVGBE_RX_CRC_ERROR (0 << 1)
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#define MVGBE_RX_OVERRUN_ERROR (1 << 1)
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#define MVGBE_RX_MAX_FRAME_LEN_ERROR (2 << 1)
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#define MVGBE_RX_RESOURCE_ERROR (3 << 1)
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#define MVGBE_RX_L4_CHECKSUM_MASK (0xffff << 3)
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#define MVGBE_RX_VLAN_TAGGED_FRAME (1 << 19)
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#define MVGBE_RX_BPDU_FRAME (1 << 20)
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#define MVGBE_RX_L4_TYPE_MASK (3 << 21)
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#define MVGBE_RX_L4_TYPE_TCP (0 << 21)
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#define MVGBE_RX_L4_TYPE_UDP (1 << 21)
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#define MVGBE_RX_L4_TYPE_OTHER (2 << 21)
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#define MVGBE_RX_NOT_LLC_SNAP_FORMAT (1 << 23)
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#define MVGBE_RX_IP_FRAME_TYPE (1 << 24)
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#define MVGBE_RX_IP_HEADER_OK (1 << 25)
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#define MVGBE_RX_LAST_DESC (1 << 26)
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#define MVGBE_RX_FIRST_DESC (1 << 27)
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#define MVGBE_RX_UNKNOWN_DA (1 << 28)
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#define MVGBE_RX_ENABLE_INTERRUPT (1 << 29)
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#define MVGBE_RX_L4_CHECKSUM_OK (1 << 30)
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#define MVGBE_RX_IP_FRAGMENT (1 << 2)
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#endif /* _MVGEREG_H_ */
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