507 lines
13 KiB
C
507 lines
13 KiB
C
/* $NetBSD: if_mvxpevar.h,v 1.9 2022/04/04 19:33:45 andvar Exp $ */
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/*
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* Copyright (c) 2015 Internet Initiative Japan Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IF_MVXPEVAR_H_
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#define _IF_MVXPEVAR_H_
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#include <net/if.h>
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#include <dev/marvell/mvxpbmvar.h>
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/*
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* Limit of packet sizes.
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*/
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#define MVXPE_HWHEADER_SIZE 2 /* Marvell Header */
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#define MVXPE_MRU 2000 /* Max Receive Unit */
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#define MVXPE_MTU MVXPE_MRU /* Max Transmit Unit */
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/*
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* Default limit of queue length
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*
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* queue 0 is lowest priority and queue 7 is highest priority.
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*
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* XXX: packet classifier is not implement yet
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*/
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#define MVXPE_RX_QUEUE_LIMIT_0 IFQ_MAXLEN
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#define MVXPE_RX_QUEUE_LIMIT_1 8
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#define MVXPE_RX_QUEUE_LIMIT_2 8
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#define MVXPE_RX_QUEUE_LIMIT_3 8
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#define MVXPE_RX_QUEUE_LIMIT_4 8
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#define MVXPE_RX_QUEUE_LIMIT_5 8
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#define MVXPE_RX_QUEUE_LIMIT_6 8
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#define MVXPE_RX_QUEUE_LIMIT_7 8
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#define MVXPE_TX_QUEUE_LIMIT_0 IFQ_MAXLEN
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#define MVXPE_TX_QUEUE_LIMIT_1 8
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#define MVXPE_TX_QUEUE_LIMIT_2 8
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#define MVXPE_TX_QUEUE_LIMIT_3 8
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#define MVXPE_TX_QUEUE_LIMIT_4 8
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#define MVXPE_TX_QUEUE_LIMIT_5 8
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#define MVXPE_TX_QUEUE_LIMIT_6 8
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#define MVXPE_TX_QUEUE_LIMIT_7 8
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/* interrupt is triggered when corossing (queuelen / RATIO) */
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#define MVXPE_RXTH_RATIO 8
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#define MVXPE_RXTH_REFILL_RATIO 2
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#define MVXPE_TXTH_RATIO 8
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/*
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* Device Register access
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*/
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#define MVXPE_READ(sc, reg) \
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bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
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#define MVXPE_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
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#define MVXPE_READ_REGION(sc, reg, val, c) \
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bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
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#define MVXPE_WRITE_REGION(sc, reg, val, c) \
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bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
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#define MVXPE_READ_MIB(sc, reg) \
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bus_space_read_4((sc)->sc_iot, (sc)->sc_mibh, (reg))
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#define MVXPE_IS_LINKUP(sc) \
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(MVXPE_READ((sc), MVXPE_PSR) & MVXPE_PSR_LINKUP)
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#define MVXPE_IS_QUEUE_BUSY(queues, q) \
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((((queues) >> (q)) & 0x1))
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/*
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* EEE: Lower Power Idle config
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* Default timer is duration of MTU sized frame transmission.
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* The timer can be negotiated by LLDP protocol, but we have no
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* support.
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*/
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#define MVXPE_LPI_TS (MVXPE_MRU * 8 / 1000) /* [us] */
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#define MVXPE_LPI_TW (MVXPE_MRU * 8 / 1000) /* [us] */
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#define MVXPE_LPI_LI (MVXPE_MRU * 8 / 1000) /* [us] */
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/*
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* DMA Descriptor
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*
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* the ethernet device has 8 rx/tx DMA queues. each of queue has its own
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* descriptor list. descriptors are simply index by counter inside the device.
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*/
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#define MVXPE_TX_RING_CNT IFQ_MAXLEN
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#define MVXPE_TX_RING_MSK (MVXPE_TX_RING_CNT - 1)
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#define MVXPE_TX_RING_NEXT(x) (((x) + 1) & MVXPE_TX_RING_MSK)
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#define MVXPE_RX_RING_CNT IFQ_MAXLEN
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#define MVXPE_RX_RING_MSK (MVXPE_RX_RING_CNT - 1)
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#define MVXPE_RX_RING_NEXT(x) (((x) + 1) & MVXPE_RX_RING_MSK)
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#define MVXPE_TX_SEGLIMIT 32
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struct mvxpe_rx_ring {
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/* Real descriptors array. shared by RxDMA */
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struct mvxpe_rx_desc *rx_descriptors;
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bus_dmamap_t rx_descriptors_map;
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/* Management entries for each of descriptors */
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struct mvxpe_rx_handle {
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struct mvxpe_rx_desc *rxdesc_va;
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off_t rxdesc_off; /* from rx_descriptors[0] */
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struct mvxpbm_chunk *chunk;
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} rx_handle[MVXPE_RX_RING_CNT];
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/* locks */
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kmutex_t rx_ring_mtx;
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/* Index */
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int rx_dma;
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int rx_cpu;
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/* Limit */
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int rx_queue_len;
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int rx_queue_th_received;
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int rx_queue_th_free;
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int rx_queue_th_time; /* [Tclk] */
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};
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struct mvxpe_tx_ring {
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/* Real descriptors array. shared by TxDMA */
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struct mvxpe_tx_desc *tx_descriptors;
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bus_dmamap_t tx_descriptors_map;
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/* Management entries for each of descriptors */
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struct mvxpe_tx_handle {
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struct mvxpe_tx_desc *txdesc_va;
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off_t txdesc_off; /* from tx_descriptors[0] */
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struct mbuf *txdesc_mbuf;
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bus_dmamap_t txdesc_mbuf_map;
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} tx_handle[MVXPE_TX_RING_CNT];
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/* locks */
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kmutex_t tx_ring_mtx;
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/* Index */
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int tx_used;
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int tx_dma;
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int tx_cpu;
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/* Limit */
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int tx_queue_len;
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int tx_queue_th_free;
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};
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static __inline int
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tx_counter_adv(int ctr, int n)
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{
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/* XXX: lock or atomic */
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ctr += n;
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while (ctr >= MVXPE_TX_RING_CNT)
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ctr -= MVXPE_TX_RING_CNT;
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return ctr;
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}
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static __inline int
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rx_counter_adv(int ctr, int n)
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{
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/* XXX: lock or atomic */
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ctr += n;
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while (ctr >= MVXPE_TX_RING_CNT)
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ctr -= MVXPE_TX_RING_CNT;
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return ctr;
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}
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/*
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* Timeout control
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*/
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#define MVXPE_PHY_TIMEOUT 10000 /* msec */
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#define RX_DISABLE_TIMEOUT 0x1000000 /* times */
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#define TX_DISABLE_TIMEOUT 0x1000000 /* times */
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#define TX_FIFO_EMPTY_TIMEOUT 0x1000000 /* times */
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/*
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* Event counter
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*/
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#ifdef MVXPE_EVENT_COUNTERS
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#define MVXPE_EVCNT_INCR(ev) (ev)->ev_count++
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#define MVXPE_EVCNT_ADD(ev, val) (ev)->ev_count += (val)
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#else
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#define MVXPE_EVCNT_INCR(ev) /* nothing */
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#define MVXPE_EVCNT_ADD(ev, val) /* nothing */
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#endif
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struct mvxpe_evcnt {
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/*
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* Master Interrupt Handler
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*/
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struct evcnt ev_i_rxtxth;
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struct evcnt ev_i_rxtx;
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struct evcnt ev_i_misc;
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/*
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* RXTXTH Interrupt
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*/
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struct evcnt ev_rxtxth_txerr;
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/*
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* MISC Interrupt
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*/
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struct evcnt ev_misc_phystatuschng;
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struct evcnt ev_misc_linkchange;
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struct evcnt ev_misc_iae;
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struct evcnt ev_misc_rxoverrun;
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struct evcnt ev_misc_rxcrc;
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struct evcnt ev_misc_rxlargepacket;
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struct evcnt ev_misc_txunderrun;
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struct evcnt ev_misc_prbserr;
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struct evcnt ev_misc_srse;
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struct evcnt ev_misc_txreq;
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/*
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* RxTx Interrupt
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*/
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struct evcnt ev_rxtx_rreq;
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struct evcnt ev_rxtx_rpq;
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struct evcnt ev_rxtx_tbrq;
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struct evcnt ev_rxtx_rxtxth;
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struct evcnt ev_rxtx_txerr;
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struct evcnt ev_rxtx_misc;
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/*
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* Link
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*/
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struct evcnt ev_link_up;
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struct evcnt ev_link_down;
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/*
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* Rx Descriptor
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*/
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struct evcnt ev_rxd_ce;
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struct evcnt ev_rxd_or;
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struct evcnt ev_rxd_mf;
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struct evcnt ev_rxd_re;
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struct evcnt ev_rxd_scat;
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/*
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* Tx Descriptor
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*/
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struct evcnt ev_txd_lc;
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struct evcnt ev_txd_ur;
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struct evcnt ev_txd_rl;
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struct evcnt ev_txd_oth;
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/*
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* Status Registers
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*/
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struct evcnt ev_reg_pdfc; /* Rx Port Discard Frame Counter */
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struct evcnt ev_reg_pofc; /* Rx Port Overrun Frame Counter */
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struct evcnt ev_reg_txbadfcs; /* Tx BAD FCS Counter */
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struct evcnt ev_reg_txdropped; /* Tx Dropped Counter */
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struct evcnt ev_reg_lpic;
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/* Device Driver Errors */
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struct evcnt ev_drv_wdogsoft;
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struct evcnt ev_drv_txerr;
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struct evcnt ev_drv_rxq[MVXPE_QUEUE_SIZE];
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struct evcnt ev_drv_rxqe[MVXPE_QUEUE_SIZE];
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struct evcnt ev_drv_txq[MVXPE_QUEUE_SIZE];
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struct evcnt ev_drv_txqe[MVXPE_QUEUE_SIZE];
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};
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/*
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* Debug
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*/
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#ifdef MVXPE_DEBUG
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#define DPRINTF(fmt, ...) \
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do { \
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if (mvxpe_debug >= 1) { \
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printf("%s: ", __func__); \
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printf((fmt), ##__VA_ARGS__); \
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} \
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} while (/*CONSTCOND*/0)
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#define DPRINTFN(level , fmt, ...) \
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do { \
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if (mvxpe_debug >= (level)) { \
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printf("%s: ", __func__); \
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printf((fmt), ##__VA_ARGS__); \
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} \
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} while (/*CONSTCOND*/0)
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#define DPRINTDEV(dev, level, fmt, ...) \
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do { \
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if (mvxpe_debug >= (level)) { \
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device_printf((dev), \
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"%s: "fmt , __func__, ##__VA_ARGS__); \
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} \
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} while (/*CONSTCOND*/0)
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#define DPRINTSC(sc, level, fmt, ...) \
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do { \
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device_t dev = (sc)->sc_dev; \
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if (mvxpe_debug >= (level)) { \
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device_printf(dev, \
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"%s: " fmt, __func__, ##__VA_ARGS__); \
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} \
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} while (/*CONSTCOND*/0)
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#define DPRINTIFNET(ifp, level, fmt, ...) \
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do { \
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const char *xname = (ifp)->if_xname; \
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if (mvxpe_debug >= (level)) { \
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printf("%s: %s: " fmt, xname, __func__, ##__VA_ARGS__);\
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} \
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} while (/*CONSTCOND*/0)
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#define DPRINTIFNET(ifp, level, fmt, ...) \
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do { \
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const char *xname = (ifp)->if_xname; \
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if (mvxpe_debug >= (level)) { \
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printf("%s: %s: " fmt, xname, __func__, ##__VA_ARGS__);\
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} \
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} while (/*CONSTCOND*/0)
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#define DPRINTPRXS(level, q) \
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do { \
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uint32_t _reg = MVXPE_READ(sc, MVXPE_PRXS(q)); \
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if (mvxpe_debug >= (level)) { \
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printf("PRXS(queue %d) %#x: Occupied %d, NoOccupied %d.\n", \
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q, _reg, MVXPE_PRXS_GET_ODC(_reg), \
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MVXPE_PRXS_GET_NODC(_reg)); \
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} \
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} while (/*CONSTCOND*/0)
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#else
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#define DPRINTF(fmt, ...)
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#define DPRINTFN(level, fmt, ...)
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#define DPRINTDEV(dev, level, fmt, ...)
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#define DPRINTSC(sc, level, fmt, ...)
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#define DPRINTIFNET(ifp, level, fmt, ...)
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#define DPRINTPRXS(level, reg)
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#endif
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#define KASSERT_SC_MTX(sc) \
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KASSERT(mutex_owned(&(sc)->sc_mtx))
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#define KASSERT_BM_MTX(sc) \
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KASSERT(mutex_owned(&(sc)->sc_bm.bm_mtx))
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#define KASSERT_RX_MTX(sc, q) \
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KASSERT(mutex_owned(&(sc)->sc_rx_ring[(q)].rx_ring_mtx))
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#define KASSERT_TX_MTX(sc, q) \
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KASSERT(mutex_owned(&(sc)->sc_tx_ring[(q)].tx_ring_mtx))
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/*
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* Configuration parameters
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*/
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struct mvxpe_conf {
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int cf_lpi; /* EEE Low Power IDLE enable */
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int cf_fc; /* Flow Control enable */
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};
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/*
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* sysctl(9) parameters
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*/
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struct mvxpe_softc;
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struct mvxpe_sysctl_queue {
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struct mvxpe_softc *sc;
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int rxtx;
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int queue;
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};
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#define MVXPE_SYSCTL_RX 0
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#define MVXPE_SYSCTL_TX 1
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struct mvxpe_sysctl_mib {
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struct mvxpe_softc *sc;
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int index;
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uint64_t counter;
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};
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/*
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* Ethernet Device main context
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*/
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struct mvxpe_softc {
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device_t sc_dev;
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int sc_port;
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uint32_t sc_version;
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/*
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* sc_mtx must be held by interface functions to/from
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* other frameworks. interrupt handler, sysctl handler,
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* ioctl handler, and so on.
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*/
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kmutex_t sc_mtx;
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/*
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* Ethernet facilities
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*/
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struct ethercom sc_ethercom;
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struct mii_data sc_mii;
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u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */
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u_short sc_if_flags;
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int sc_wdogsoft;
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/*
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* Configuration Parameters
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*/
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struct mvxpe_conf sc_cf;
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/*
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* I/O Spaces
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*/
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh; /* all registers handle */
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bus_space_handle_t sc_mibh; /* mib counter handle */
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/*
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* DMA Spaces
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*/
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bus_dma_tag_t sc_dmat;
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struct mvxpe_rx_ring sc_rx_ring[MVXPE_QUEUE_SIZE];
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struct mvxpe_tx_ring sc_tx_ring[MVXPE_QUEUE_SIZE];
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int sc_tx_pending; /* total number of tx pkt */
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/*
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* Software Buffer Manager
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*/
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struct mvxpbm_softc *sc_bm;
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/*
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* Maintenance clock
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*/
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callout_t sc_tick_ch; /* tick callout */
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/*
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* Link State control
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*/
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uint32_t sc_linkstate;
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/*
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* Act as Rndom source
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*/
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krndsource_t sc_rnd_source;
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/*
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* Sysctl interfaces
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*/
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struct sysctllog *sc_mvxpe_clog;
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struct mvxpe_sysctl_queue sc_sysctl_rx_queue[MVXPE_QUEUE_SIZE];
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struct mvxpe_sysctl_queue sc_sysctl_tx_queue[MVXPE_QUEUE_SIZE];
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/*
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* MIB counter
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*/
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size_t sc_sysctl_mib_size;
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struct mvxpe_sysctl_mib *sc_sysctl_mib;
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#ifdef MVXPE_EVENT_COUNTERS
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/*
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* Event counter
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*/
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struct mvxpe_evcnt sc_ev;
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#endif
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};
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#define MVXPE_RX_RING_MEM_VA(sc, q) \
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((sc)->sc_rx_ring[(q)].rx_descriptors)
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#define MVXPE_RX_RING_MEM_PA(sc, q) \
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((sc)->sc_rx_ring[(q)].rx_descriptors_map->dm_segs[0].ds_addr)
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#define MVXPE_RX_RING_MEM_MAP(sc, q) \
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((sc)->sc_rx_ring[(q)].rx_descriptors_map)
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#define MVXPE_RX_RING(sc, q) \
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(&(sc)->sc_rx_ring[(q)])
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#define MVXPE_RX_HANDLE(sc, q, i) \
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(&(sc)->sc_rx_ring[(q)].rx_handle[(i)])
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#define MVXPE_RX_DESC(sc, q, i) \
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((sc)->sc_rx_ring[(q)].rx_handle[(i)].rxdesc_va)
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#define MVXPE_RX_DESC_OFF(sc, q, i) \
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((sc)->sc_rx_ring[(q)].rx_handle[(i)].rxdesc_off)
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#define MVXPE_RX_PKTBUF(sc, q, i) \
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((sc)->sc_rx_ring[(q)].rx_handle[(i)].chunk)
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#define MVXPE_TX_RING_MEM_VA(sc, q) \
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((sc)->sc_tx_ring[(q)].tx_descriptors)
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#define MVXPE_TX_RING_MEM_PA(sc, q) \
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((sc)->sc_tx_ring[(q)].tx_descriptors_map->dm_segs[0].ds_addr)
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#define MVXPE_TX_RING_MEM_MAP(sc, q) \
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((sc)->sc_tx_ring[(q)].tx_descriptors_map)
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#define MVXPE_TX_RING(sc, q) \
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(&(sc)->sc_tx_ring[(q)])
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#define MVXPE_TX_HANDLE(sc, q, i) \
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(&(sc)->sc_tx_ring[(q)].tx_handle[(i)])
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#define MVXPE_TX_DESC(sc, q, i) \
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((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_va)
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#define MVXPE_TX_DESC_OFF(sc, q, i) \
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((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_off)
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#define MVXPE_TX_MBUF(sc, q, i) \
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((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_mbuf)
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#define MVXPE_TX_MAP(sc, q, i) \
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((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_mbuf_map)
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#endif /* _IF_MVXPEVAR_H_ */
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