617 lines
16 KiB
C
617 lines
16 KiB
C
/* $NetBSD: gtpci.c,v 1.38 2022/09/25 18:45:45 thorpej Exp $ */
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/*
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* Copyright (c) 2008, 2009 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.38 2022/09/25 18:45:45 thorpej Exp $");
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#include "opt_pci.h"
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#include "pci.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <prop/proplib.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include <dev/marvell/gtpcireg.h>
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#include <dev/marvell/gtpcivar.h>
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#include <dev/marvell/marvellreg.h>
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#include <dev/marvell/marvellvar.h>
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#include <machine/pci_machdep.h>
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#include "locators.h"
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#define GTPCI_READ(sc, r) \
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bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit))
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#define GTPCI_WRITE(sc, r, v) \
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bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit), (v))
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#define GTPCI_WRITE_AC(sc, r, n, v) \
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bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit, (n)), (v))
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static int gtpci_match(device_t, struct cfdata *, void *);
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static void gtpci_attach(device_t, device_t, void *);
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static void gtpci_init(struct gtpci_softc *, struct gtpci_prot *);
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static void gtpci_barinit(struct gtpci_softc *);
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static void gtpci_protinit(struct gtpci_softc *, struct gtpci_prot *);
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#if NPCI > 0
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static void gtpci_pci_config(struct gtpci_softc *, bus_space_tag_t,
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bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t,
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u_long, u_long, u_long, u_long, int);
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#endif
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CFATTACH_DECL_NEW(gtpci_gt, sizeof(struct gtpci_softc),
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gtpci_match, gtpci_attach, NULL, NULL);
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CFATTACH_DECL_NEW(gtpci_mbus, sizeof(struct gtpci_softc),
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gtpci_match, gtpci_attach, NULL, NULL);
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/* ARGSUSED */
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static int
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gtpci_match(device_t parent, struct cfdata *match, void *aux)
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{
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struct marvell_attach_args *mva = aux;
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if (strcmp(mva->mva_name, match->cf_name) != 0)
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return 0;
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if (mva->mva_unit == MVA_UNIT_DEFAULT)
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return 0;
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switch (mva->mva_model) {
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case MARVELL_DISCOVERY:
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case MARVELL_DISCOVERY_II:
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case MARVELL_DISCOVERY_III:
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#if 0 /* XXXXX */
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case MARVELL_DISCOVERY_LT:
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case MARVELL_DISCOVERY_V:
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case MARVELL_DISCOVERY_VI:
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#endif
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if (mva->mva_offset != MVA_OFFSET_DEFAULT)
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return 0;
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}
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mva->mva_size = GTPCI_SIZE;
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return 1;
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}
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/* ARGSUSED */
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static void
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gtpci_attach(device_t parent, device_t self, void *aux)
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{
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struct gtpci_softc *sc = device_private(self);
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struct marvell_attach_args *mva = aux;
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struct gtpci_prot *gtpci_prot;
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prop_dictionary_t dict = device_properties(self);
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prop_object_t prot;
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#if NPCI > 0
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prop_object_t pc, iot, memt;
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prop_array_t int2gpp;
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prop_object_t gpp;
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pci_chipset_tag_t gtpci_chipset;
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bus_space_tag_t gtpci_io_bs_tag, gtpci_mem_bs_tag;
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uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0;
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int cl_size = 0, intr;
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#endif
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aprint_normal(": Marvell PCI Interface\n");
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aprint_naive("\n");
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prot = prop_dictionary_get(dict, "prot");
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if (prot != NULL) {
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KASSERT(prop_object_type(prot) == PROP_TYPE_DATA);
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gtpci_prot = __UNCONST(prop_data_data_nocopy(prot));
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} else {
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aprint_verbose_dev(self, "no protection property\n");
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gtpci_prot = NULL;
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}
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#if NPCI > 0
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iot = prop_dictionary_get(dict, "io-bus-tag");
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if (iot != NULL) {
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KASSERT(prop_object_type(iot) == PROP_TYPE_DATA);
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gtpci_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot));
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} else {
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aprint_error_dev(self, "no io-bus-tag property\n");
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gtpci_io_bs_tag = NULL;
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}
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memt = prop_dictionary_get(dict, "mem-bus-tag");
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if (memt != NULL) {
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KASSERT(prop_object_type(memt) == PROP_TYPE_DATA);
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gtpci_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt));
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} else {
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aprint_error_dev(self, "no mem-bus-tag property\n");
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gtpci_mem_bs_tag = NULL;
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}
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pc = prop_dictionary_get(dict, "pci-chipset");
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if (pc == NULL) {
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aprint_error_dev(self, "no pci-chipset property\n");
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return;
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}
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KASSERT(prop_object_type(pc) == PROP_TYPE_DATA);
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gtpci_chipset = __UNCONST(prop_data_data_nocopy(pc));
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#ifdef PCI_NETBSD_CONFIGURE
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if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) {
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aprint_error_dev(self, "no iostart property\n");
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return;
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}
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if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) {
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aprint_error_dev(self, "no ioend property\n");
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return;
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}
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if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) {
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aprint_error_dev(self, "no memstart property\n");
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return;
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}
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if (!prop_dictionary_get_uint64(dict, "memend", &memend)) {
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aprint_error_dev(self, "no memend property\n");
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return;
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}
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if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) {
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aprint_error_dev(self, "no cache-line-size property\n");
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return;
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}
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#endif
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#endif
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sc->sc_dev = self;
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sc->sc_model = mva->mva_model;
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sc->sc_rev = mva->mva_revision;
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sc->sc_unit = mva->mva_unit;
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sc->sc_iot = mva->mva_iot;
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if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
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(mva->mva_offset != MVA_OFFSET_DEFAULT) ? mva->mva_offset : 0,
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mva->mva_size, &sc->sc_ioh)) {
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aprint_error_dev(self, "can't map registers\n");
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return;
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}
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sc->sc_pc = gtpci_chipset;
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gtpci_init(sc, gtpci_prot);
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#if NPCI > 0
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int2gpp = prop_dictionary_get(dict, "int2gpp");
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if (int2gpp != NULL) {
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if (prop_object_type(int2gpp) != PROP_TYPE_ARRAY) {
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aprint_error_dev(self, "int2gpp not an array\n");
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return;
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}
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aprint_normal_dev(self, "use interrupt pin:");
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for (intr = PCI_INTERRUPT_PIN_A;
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intr <= PCI_INTERRUPT_PIN_D &&
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intr < prop_array_count(int2gpp);
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intr++) {
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gpp = prop_array_get(int2gpp, intr);
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if (prop_object_type(gpp) != PROP_TYPE_NUMBER) {
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aprint_error_dev(self,
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"int2gpp[%d] not an number\n", intr);
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return;
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}
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aprint_normal(" %d",
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(int)prop_number_integer_value(gpp));
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}
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aprint_normal("\n");
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}
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gtpci_pci_config(sc, gtpci_io_bs_tag, gtpci_mem_bs_tag, mva->mva_dmat,
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gtpci_chipset, iostart, ioend, memstart, memend, cl_size);
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#endif
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}
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static void
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gtpci_init(struct gtpci_softc *sc, struct gtpci_prot *prot)
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{
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uint32_t reg;
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/* First, all disable. Also WA CQ 4382 (bit15 must set 1)*/
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GTPCI_WRITE(sc, GTPCI_BARE, GTPCI_BARE_ALLDISABLE | (1 << 15));
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/* Enable Internal Arbiter */
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reg = GTPCI_READ(sc, GTPCI_AC);
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reg |= GTPCI_AC_EN;
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GTPCI_WRITE(sc, GTPCI_AC, reg);
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gtpci_barinit(sc);
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if (prot != NULL)
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gtpci_protinit(sc, prot);
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reg = GTPCI_READ(sc, GTPCI_ADC);
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reg |= GTPCI_ADC_REMAPWRDIS;
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GTPCI_WRITE(sc, GTPCI_ADC, reg);
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/* enable CPU-2-PCI ordering */
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reg = GTPCI_READ(sc, GTPCI_C);
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reg |= GTPCI_C_CPU2PCIORDERING;
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GTPCI_WRITE(sc, GTPCI_C, reg);
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}
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static void
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gtpci_barinit(struct gtpci_softc *sc)
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{
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static const struct {
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int tag;
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int bars[2]; /* BAR Size registers */
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int bare; /* Bits of Base Address Registers Enable */
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int func;
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int balow;
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int bahigh;
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} maps[] = {
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{ MARVELL_TAG_SDRAM_CS0,
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{ GTPCI_CS0BARS(0), GTPCI_CS0BARS(1) },
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GTPCI_BARE_CS0EN, 0, 0x10, 0x14 },
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{ MARVELL_TAG_SDRAM_CS1,
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{ GTPCI_CS1BARS(0), GTPCI_CS1BARS(1) },
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GTPCI_BARE_CS1EN, 0, 0x18, 0x1c },
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{ MARVELL_TAG_SDRAM_CS2,
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{ GTPCI_CS2BARS(0), GTPCI_CS2BARS(1) },
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GTPCI_BARE_CS2EN, 1, 0x10, 0x14 },
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{ MARVELL_TAG_SDRAM_CS3,
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{ GTPCI_CS3BARS(0), GTPCI_CS3BARS(1) },
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GTPCI_BARE_CS3EN, 1, 0x18, 0x1c },
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#if 0
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{ ORION_TARGETID_INTERNALREG,
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{ -1, -1 },
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GTPCI_BARE_INTMEMEN, 0, 0x20, 0x24 },
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{ ORION_TARGETID_DEVICE_CS0,
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{ GTPCI_DCS0BARS(0), GTPCI_DCS0BARS(1) },
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GTPCI_BARE_DEVCS0EN, 2, 0x10, 0x14 },
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{ ORION_TARGETID_DEVICE_CS1,
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{ GTPCI_DCS1BARS(0), GTPCI_DCS1BARS(1) },
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GTPCI_BARE_DEVCS1EN, 2, 0x18, 0x1c },
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{ ORION_TARGETID_DEVICE_CS2,
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{ GTPCI_DCS2BARS(0), GTPCI_DCS2BARS(1) },
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GTPCI_BARE_DEVCS2EN, 2, 0x20, 0x24 },
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{ ORION_TARGETID_DEVICE_BOOTCS,
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{ GTPCI_BCSBARS(0), GTPCI_BCSBARS(1) },
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GTPCI_BARE_BOOTCSEN, 3, 0x18, 0x1c },
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{ P2P Mem0 BAR,
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{ GTPCI_P2PM0BARS(0), GTPCI_P2PM0BARS(1) },
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GTPCI_BARE_P2PMEM0EN, 4, 0x10, 0x14 },
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{ P2P I/O BAR,
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{ GTPCI_P2PIOBARS(0), GTPCI_P2PIOBARS(1) },
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GTPCI_BARE_P2PIO0EN, 4, 0x20, 0x24 },
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{ Expansion ROM BAR,
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{ GTPCI_EROMBARS(0), GTPCI_EROMBARS(1) },
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0, },
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#endif
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{ MARVELL_TAG_UNDEFINED,
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{ -1, -1 },
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-1, -1, 0x00, 0x00 },
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};
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device_t pdev = device_parent(sc->sc_dev);
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uint64_t base;
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uint32_t size, bare;
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int map, rv;
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bare = GTPCI_BARE_ALLDISABLE;
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for (map = 0; maps[map].tag != MARVELL_TAG_UNDEFINED; map++) {
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rv = marvell_winparams_by_tag(pdev, maps[map].tag, NULL, NULL,
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&base, &size);
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if (rv != 0 || size == 0)
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continue;
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if (maps[map].bars[sc->sc_unit] != -1)
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bus_space_write_4(sc->sc_iot, sc->sc_ioh,
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maps[map].bars[sc->sc_unit], GTPCI_BARSIZE(size));
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bare &= ~maps[map].bare;
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#if 0 /* shall move to pchb(4)? */
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if (maps[map].func != -1) {
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pcitag_t tag;
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pcireg_t reg;
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int dev = GTPCI_P2PC_DEVNUM(p2pc);
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int bus = GTPCI_P2PC_BUSNUMBER(p2pc);
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uint32_t p2pc = GTPCI_READ(sc, GTPCI_P2PC);
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tag = gtpci_make_tag(NULL, bus, dev, maps[map].func);
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reg = gtpci_conf_read(sc, tag, maps[map].balow);
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reg &= ~GTPCI_BARLOW_MASK;
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reg |= GTPCI_BARLOW_BASE(base);
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gtpci_conf_write(sc, tag, maps[map].balow, reg);
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reg = gtpci_conf_read(sc, tag, maps[map].bahigh);
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reg = (base >> 16) >> 16;
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gtpci_conf_write(sc, tag, maps[map].bahigh, reg);
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}
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#endif
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}
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GTPCI_WRITE(sc, GTPCI_BARE, bare);
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}
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static void
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gtpci_protinit(struct gtpci_softc *sc, struct gtpci_prot *ac_flags)
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{
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enum {
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gt642xx = 0,
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mv643xx,
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arm_soc,
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};
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const struct gtpci_ac_rshift {
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uint32_t base_rshift;
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uint32_t size_rshift;
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} ac_rshifts[] = {
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{ 20, 20, }, /* GT642xx */
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{ 0, 0, }, /* MV643xx and after */
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{ 0, 0, }, /* ARM SoC */
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};
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const uint32_t prot_tags[] = {
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MARVELL_TAG_SDRAM_CS0,
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MARVELL_TAG_SDRAM_CS1,
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MARVELL_TAG_SDRAM_CS2,
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MARVELL_TAG_SDRAM_CS3,
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MARVELL_TAG_UNDEFINED
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};
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device_t pdev = device_parent(sc->sc_dev);
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uint64_t acbase, base;
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uint32_t acsize, size;
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int base_rshift, size_rshift, acbl_flags, acs_flags;
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int prot, rv, p, t;
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switch (sc->sc_model) {
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case MARVELL_DISCOVERY:
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p = gt642xx;
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break;
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case MARVELL_DISCOVERY_II:
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case MARVELL_DISCOVERY_III:
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#if 0
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case MARVELL_DISCOVERY_LT:
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case MARVELL_DISCOVERY_V:
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case MARVELL_DISCOVERY_VI:
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#endif
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p = mv643xx;
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break;
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default:
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p = arm_soc;
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break;
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}
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base_rshift = ac_rshifts[p].base_rshift;
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size_rshift = ac_rshifts[p].size_rshift;
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acbl_flags = ac_flags->acbl_flags;
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acs_flags = ac_flags->acs_flags;
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t = 0;
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for (prot = 0; prot < GTPCI_NPCIAC; prot++) {
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acbase = acsize = 0;
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for ( ; prot_tags[t] != MARVELL_TAG_UNDEFINED; t++) {
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rv = marvell_winparams_by_tag(pdev, prot_tags[t],
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NULL, NULL, &base, &size);
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if (rv != 0 || size == 0)
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continue;
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if (acsize == 0 || base + size == acbase)
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acbase = base;
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else if (acbase + acsize != base)
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break;
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acsize += size;
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}
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if (acsize != 0) {
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GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot,
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((acbase & 0xffffffff) >> base_rshift) | acbl_flags);
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GTPCI_WRITE_AC(sc, GTPCI_ACBH, prot,
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(acbase >> 32) & 0xffffffff);
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GTPCI_WRITE_AC(sc, GTPCI_ACS, prot,
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((acsize - 1) >> size_rshift) | acs_flags);
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} else {
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GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot, 0);
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GTPCI_WRITE_AC(sc, GTPCI_ACBH, prot, 0);
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GTPCI_WRITE_AC(sc, GTPCI_ACS, prot, 0);
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}
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}
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return;
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}
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#if NPCI > 0
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static void
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gtpci_pci_config(struct gtpci_softc *sc, bus_space_tag_t iot,
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bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc,
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u_long iostart, u_long ioend, u_long memstart, u_long memend,
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int cacheline_size)
|
|
{
|
|
struct pcibus_attach_args pba;
|
|
uint32_t p2pc, command;
|
|
|
|
p2pc = GTPCI_READ(sc, GTPCI_P2PC);
|
|
|
|
#ifdef PCI_NETBSD_CONFIGURE
|
|
struct pciconf_resources *pcires = pciconf_resource_init();
|
|
|
|
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
|
|
iostart, (ioend - iostart) + 1);
|
|
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
|
|
memstart, (memend - memstart) + 1);
|
|
|
|
pci_configure_bus(pc, pcires,
|
|
GTPCI_P2PC_BUSNUMBER(p2pc), cacheline_size);
|
|
|
|
pciconf_resource_fini(pcires);
|
|
#endif
|
|
|
|
pba.pba_iot = iot;
|
|
pba.pba_memt = memt;
|
|
pba.pba_dmat = dmat;
|
|
pba.pba_dmat64 = NULL;
|
|
pba.pba_pc = pc;
|
|
if (iot == NULL || memt == NULL) {
|
|
pba.pba_flags = 0;
|
|
aprint_error_dev(sc->sc_dev, "");
|
|
if (iot == NULL)
|
|
aprint_error("io ");
|
|
else
|
|
pba.pba_flags |= PCI_FLAGS_IO_OKAY;
|
|
if (iot == NULL && memt == NULL)
|
|
aprint_error("and ");
|
|
if (memt == NULL)
|
|
aprint_error("mem");
|
|
else
|
|
pba.pba_flags |= PCI_FLAGS_MEM_OKAY;
|
|
aprint_error(" access disabled\n");
|
|
} else
|
|
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
|
|
command = GTPCI_READ(sc, GTPCI_C);
|
|
if (command & GTPCI_C_MRDMUL)
|
|
pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
|
|
if (command & GTPCI_C_MRDLINE)
|
|
pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
|
|
pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
|
|
pba.pba_bus = GTPCI_P2PC_BUSNUMBER(p2pc);
|
|
pba.pba_bridgetag = NULL;
|
|
config_found(sc->sc_dev, &pba, NULL, CFARGS_NONE);
|
|
}
|
|
|
|
|
|
/*
|
|
* Dependent code of PCI Interface of Marvell
|
|
*/
|
|
|
|
/* ARGSUSED */
|
|
void
|
|
gtpci_attach_hook(device_t parent, device_t self,
|
|
struct pcibus_attach_args *pba)
|
|
{
|
|
|
|
/* Nothing */
|
|
}
|
|
|
|
/*
|
|
* Bit map for configuration register:
|
|
* [31] ConfigEn
|
|
* [30:24] Reserved
|
|
* [23:16] BusNum
|
|
* [15:11] DevNum
|
|
* [10: 8] FunctNum
|
|
* [ 7: 2] RegNum
|
|
* [ 1: 0] reserved
|
|
*/
|
|
|
|
/* ARGSUSED */
|
|
int
|
|
gtpci_bus_maxdevs(void *v, int busno)
|
|
{
|
|
|
|
return 32; /* 32 device/bus */
|
|
}
|
|
|
|
/* ARGSUSED */
|
|
pcitag_t
|
|
gtpci_make_tag(void *v, int bus, int dev, int func)
|
|
{
|
|
|
|
#if DIAGNOSTIC
|
|
if (bus >= 256 || dev >= 32 || func >= 8)
|
|
panic("pci_make_tag: bad request");
|
|
#endif
|
|
|
|
return (bus << 16) | (dev << 11) | (func << 8);
|
|
}
|
|
|
|
/* ARGSUSED */
|
|
void
|
|
gtpci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
|
|
{
|
|
|
|
if (bp != NULL)
|
|
*bp = (tag >> 16) & 0xff;
|
|
if (dp != NULL)
|
|
*dp = (tag >> 11) & 0x1f;
|
|
if (fp != NULL)
|
|
*fp = (tag >> 8) & 0x07;
|
|
}
|
|
|
|
pcireg_t
|
|
gtpci_conf_read(void *v, pcitag_t tag, int reg)
|
|
{
|
|
struct gtpci_softc *sc = v;
|
|
const pcireg_t addr = tag | reg;
|
|
|
|
if ((unsigned int)reg >= PCI_CONF_SIZE)
|
|
return -1;
|
|
|
|
GTPCI_WRITE(sc, GTPCI_CA, addr | GTPCI_CA_CONFIGEN);
|
|
if ((addr | GTPCI_CA_CONFIGEN) != GTPCI_READ(sc, GTPCI_CA))
|
|
return -1;
|
|
|
|
return GTPCI_READ(sc, GTPCI_CD);
|
|
}
|
|
|
|
void
|
|
gtpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
|
|
{
|
|
struct gtpci_softc *sc = v;
|
|
pcireg_t addr = tag | (reg & 0xfc);
|
|
|
|
if ((unsigned int)reg >= PCI_CONF_SIZE)
|
|
return;
|
|
|
|
GTPCI_WRITE(sc, GTPCI_CA, addr | GTPCI_CA_CONFIGEN);
|
|
if ((addr | GTPCI_CA_CONFIGEN) != GTPCI_READ(sc, GTPCI_CA))
|
|
return;
|
|
|
|
GTPCI_WRITE(sc, GTPCI_CD, data);
|
|
}
|
|
|
|
/* ARGSUSED */
|
|
int
|
|
gtpci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
|
|
{
|
|
/* Oops, We have two PCI buses. */
|
|
if (dev == 0 &&
|
|
PCI_VENDOR(id) == PCI_VENDOR_MARVELL) {
|
|
switch (PCI_PRODUCT(id)) {
|
|
case MARVELL_DISCOVERY:
|
|
case MARVELL_DISCOVERY_II:
|
|
case MARVELL_DISCOVERY_III:
|
|
#if 0
|
|
case MARVELL_DISCOVERY_LT:
|
|
case MARVELL_DISCOVERY_V:
|
|
case MARVELL_DISCOVERY_VI:
|
|
#endif
|
|
case MARVELL_ORION_1_88F5180N:
|
|
case MARVELL_ORION_1_88F5181:
|
|
case MARVELL_ORION_1_88F5182:
|
|
case MARVELL_ORION_2_88F5281:
|
|
case MARVELL_ORION_1_88W8660:
|
|
/* Don't configure us. */
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return PCI_CONF_DEFAULT;
|
|
}
|
|
#endif /* NPCI > 0 */
|