307 lines
13 KiB
C
307 lines
13 KiB
C
/* $NetBSD: gtidmacreg.h,v 1.5 2021/11/10 17:19:30 msaitoh Exp $ */
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/*
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* Copyright (c) 2008, 2009 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GTIDMACREG_H_
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#define _GTIDMACREG_H_
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/*
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* IDMA Controller Interface Registers / XOR Engine Control Registers
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*/
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#define GTIDMAC_SIZE 0x1000
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#define GTIDMAC_NWINDOW 8
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#define GTIDMAC_NREMAP 4
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#define GTIDMAC_NACCPROT 4 /* Num Access Protect */
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#define GTIDMAC_NINTRRUPT 4
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#define GTIDMAC_MAXXFER (16 * 1024 * 1024 - 1) /* 16M - 1 Byte */
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#define MVXORE_NWINDOW 8
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#define MVXORE_NREMAP 4
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#define MVXORE_MAXXFER (16 * 1024 * 1024 - 1) /* 16M - 1 Byte */
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#define MVXORE_NSRC 8
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#define GTIDMAC_CHAN2BASE(c) ((((c) & 0x4) << 6) + (((c) & 0x3) << 2))
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#define MVXORE_PORT2BASE(sc, p) \
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(((sc)->sc_gtidmac_nchan == 0 && (p) == 0) ? -0x100 : 0x000)
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#define MVXORE_CHAN2BASE(sc, c) \
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(MVXORE_PORT2BASE(sc, (c) & 0xe) + (((c) & 0x1) << 2))
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/* IDMA Descriptor Register Map */
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#define GTIDMAC_CIDMABCR(c) /* Chan IDMA Byte Count */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0800)
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#define GTIDMAC_CIDMABCR_BYTECNT_MASK 0x00ffffff
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#define GTIDMAC_CIDMABCR_BCLEFT (1 << 30) /* Left Byte Count */
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#define GTIDMAC_CIDMABCR_OWN (1 << 31) /* Ownership Bit */
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#define GTIDMAC_CIDMASAR(c) /* Chan IDMA Source Address */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0810)
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#define GTIDMAC_CIDMADAR(c) /* Chan IDMA Destination Address */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0820)
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#define GTIDMAC_CNDPR(c) /* Chan Next Descriptor Pointer */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0830)
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#define GTIDMAC_CCDPR(c) /* Chan Current Descriptor Pointer */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0870)
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/* IDMA Control Register Map */
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#define GTIDMAC_CCLR(c) /* Chan Control Low */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0840)
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#define GTIDMAC_CCLR_DBL_MASK (7 << 0) /* DstBurstLimit */
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#define GTIDMAC_CCLR_DBL_8B (0 << 0)
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#define GTIDMAC_CCLR_DBL_16B (1 << 0)
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#define GTIDMAC_CCLR_DBL_32B (3 << 0)
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#define GTIDMAC_CCLR_DBL_64B (7 << 0)
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#define GTIDMAC_CCLR_DBL_128B (4 << 0)
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#define GTIDMAC_CCLR_SRCHOLD (1 << 3) /* Source Hold */
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#define GTIDMAC_CCLR_DESTHOLD (1 << 5) /* Destination Hold */
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#define GTIDMAC_CCLR_SBL_MASK (7 << 6) /* SrcBurstLimit */
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#define GTIDMAC_CCLR_SBL_8B (0 << 6)
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#define GTIDMAC_CCLR_SBL_16B (1 << 6)
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#define GTIDMAC_CCLR_SBL_32B (3 << 6)
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#define GTIDMAC_CCLR_SBL_64B (7 << 6)
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#define GTIDMAC_CCLR_SBL_128B (4 << 6)
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#define GTIDMAC_CCLR_CHAINMODE_C (0 << 9) /* Chained Mode */
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#define GTIDMAC_CCLR_CHAINMODE_NC (1 << 9) /* Non-Chained Mode */
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#define GTIDMAC_CCLR_INTMODE (1 << 10) /* Interrupt Mode */
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#define GTIDMAC_CCLR_INTMODE_NULL (1 << 10) /* Next Desc NULL */
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#define GTIDMAC_CCLR_TRANSFERMODE_D (0 << 11) /* Transfer Mode */
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#define GTIDMAC_CCLR_TRANSFERMODE_B (1 << 11) /* Demand/Block */
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#define GTIDMAC_CCLR_CHANEN (1 << 12) /* Channel Enable */
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#define GTIDMAC_CCLR_FETCHND (1 << 13) /* Fetch Next Desc */
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#define GTIDMAC_CCLR_CHANACT (1 << 14) /* IDMA Chan Active */
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#define GTIDMAC_CCLR_CDEN (1 << 17) /* Close Desc Enable */
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#define GTIDMAC_CCLR_ABR (1 << 20) /* Channel Abort */
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#define GTIDMAC_CCLR_SADDROVR_MASK (3 << 21) /* Override Src Addr */
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#define GTIDMAC_CCLR_SADDROVR_NO (0 << 21)
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#define GTIDMAC_CCLR_SADDROVR_BAR1 (1 << 21)
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#define GTIDMAC_CCLR_SADDROVR_BAR2 (2 << 21)
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#define GTIDMAC_CCLR_SADDROVR_BAR3 (3 << 21)
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#define GTIDMAC_CCLR_NADDROVR_MASK (3 << 21) /* Override Next Addr */
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#define GTIDMAC_CCLR_NADDROVR_NO (0 << 21)
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#define GTIDMAC_CCLR_NADDROVR_BAR1 (1 << 21)
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#define GTIDMAC_CCLR_NADDROVR_BAR2 (2 << 21)
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#define GTIDMAC_CCLR_NADDROVR_BAR3 (3 << 21)
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#define GTIDMAC_CCLR_DESCMODE_64K (0 << 31)
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#define GTIDMAC_CCLR_DESCMODE_16M (1 << 31)
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#define GTIDMAC_CCHR(c) /* Chan Control High */ \
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(GTIDMAC_CHAN2BASE(c) + 0x0880)
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#define GTIDMAC_CCHR_ENDIAN_BE (0 << 0) /* big endian */
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#define GTIDMAC_CCHR_ENDIAN_LE (1 << 0) /* little endian */
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#define GTIDMAC_CCHR_DESCBYTESWAP (1 << 1) /* Desc Byte Swap */
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#define GTIDMAC_ARBR(c) (0x0860 + (((c) & 0x04) << 6)) /* Arbitrate ??*/
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#define GTIDMAC_XTOR(c) (0x08d0 + (((c) & 0x04) << 6)) /* x-bar t/o?? */
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/* IDMA Interrupt Register Map */
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#define GTIDMAC_ICR(c) (0x08c0 + (((c) & 0x04) << 6)) /* Intr Cause */
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#define GTIDMAC_IMR(c) (0x08c4 + (((c) & 0x04) << 6)) /* Intr Mask */
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#define GTIDMAC_I_BITS 8
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#define GTIDMAC_I(c, b) ((b) << (GTIDMAC_I_BITS * ((c) & 0x3)))
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#define GTIDMAC_I_COMP (1 << 0) /* Completion */
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#define GTIDMAC_I_ADDRMISS (1 << 1) /* Address Miss */
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#define GTIDMAC_I_ACCPROT (1 << 2) /* Acc Prot Violation */
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#define GTIDMAC_I_WRPROT (1 << 3) /* Write Protect */
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#define GTIDMAC_I_OWN (1 << 4) /* Ownership Violation*/
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#define GTIDMAC_EAR(c) (0x08c8 + (((c) & 0x04) << 6)) /* Err Address */
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#define GTIDMAC_ESR(c) (0x08cc + (((c) & 0x04) << 6)) /* Err Select */
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#define GTIDMAC_ESR_SEL 0x1f
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/* XOR Engine Control Registers */
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#define MVXORE_XECHAR(sc, p) /* Channel Arbiter */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0900)
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#define MVXORE_XECHAR_SLICEOWN(s, c) ((c) << (s))
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#define MVXORE_XEXCR(sc, x) /* Configuration */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0910)
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#define MVXORE_XEXCR_OM_MASK (7 << 0) /* Operation Mode */
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#define MVXORE_XEXCR_OM_XOR (0 << 0)
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#define MVXORE_XEXCR_OM_CRC32 (1 << 0)
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#define MVXORE_XEXCR_OM_DMA (2 << 0)
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#define MVXORE_XEXCR_OM_ECC (3 << 0) /* ECC cleanup ope */
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#define MVXORE_XEXCR_OM_MEMINIT (4 << 0)
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#define MVXORE_XEXCR_SBL_MASK (7 << 4) /* SrcBurstLimit */
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#define MVXORE_XEXCR_SBL_32B (2 << 4)
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#define MVXORE_XEXCR_SBL_64B (3 << 4)
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#define MVXORE_XEXCR_SBL_128B (4 << 4)
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#define MVXORE_XEXCR_DBL_MASK (7 << 8) /* SrcBurstLimit */
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#define MVXORE_XEXCR_DBL_32B (2 << 8)
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#define MVXORE_XEXCR_DBL_64B (3 << 8)
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#define MVXORE_XEXCR_DBL_128B (4 << 8)
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#define MVXORE_XEXCR_DRDRESSWP (1 << 12) /* Endianness Swap */
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#define MVXORE_XEXCR_DWRREQSWP (1 << 13) /* ReadReq/WriteRes */
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#define MVXORE_XEXCR_DESSWP (1 << 14) /* Desc read/write */
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#define MVXORE_XEXCR_REGACCPROTECT (1 << 15) /* Reg Access protect */
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#define MVXORE_XEXACTR(sc, x) /* Activation */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0920)
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#define MVXORE_XEXACTR_XESTART (1 << 0)
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#define MVXORE_XEXACTR_XESTOP (1 << 1)
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#define MVXORE_XEXACTR_XEPAUSE (1 << 2)
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#define MVXORE_XEXACTR_XERESTART (1 << 3)
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#define MVXORE_XEXACTR_XESTATUS_MASK (3 << 4)
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#define MVXORE_XEXACTR_XESTATUS_NA (0 << 4) /* not active */
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#define MVXORE_XEXACTR_XESTATUS_ACT (1 << 4) /* active */
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#define MVXORE_XEXACTR_XESTATUS_P (2 << 4) /* paused */
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/* XOR Engine Interrupt Registers */
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#define MVXORE_XEICR(sc, p) /* Interrupt Cause */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0930)
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#define MVXORE_XEIMR(sc, p) /* Interrupt Mask */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0940)
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#define MVXORE_I_BITS 16
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#define MVXORE_I(c, b) ((b) << (MVXORE_I_BITS * (c)))
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#define MVXORE_I_EOD (1 << 0) /* End of Descriptor */
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#define MVXORE_I_EOC (1 << 1) /* End of Chain */
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#define MVXORE_I_STOPPED (1 << 2)
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#define MVXORE_I_PAUSED (1 << 3)
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#define MVXORE_I_ADDRDECODE (1 << 4)
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#define MVXORE_I_ACCPROT (1 << 5) /* Access Protect */
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#define MVXORE_I_WRPROT (1 << 6) /* Write Protect */
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#define MVXORE_I_OWN (1 << 7) /* Ownership */
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#define MVXORE_I_INTPARITY (1 << 8) /* Parity error */
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#define MVXORE_I_XBAR (1 << 9) /* Crossbar Parity E */
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#define MVXORE_XEECR(sc, p) /* Error Cause */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0950)
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#define MVXORE_XEECR_ERRORTYPE_MASK 0x0000001f
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#define MVXORE_XEEAR(sc, p) /* Error Address */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0960)
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/* IDMA Address Decoding Registers Map */
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#define GTIDMAC_BARX(r) (0x0a00 + ((r) << 3)) /* Base Address x */
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#define GTIDMAC_BARX_TARGET(t) ((t) & 0xf)
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#define GTIDMAC_BARX_ATTR(a) (((a) & 0xff) << 8)
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#define GTIDMAC_BARX_BASE(b) ((b) & 0xffff0000)
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#define GTIDMAC_SRX(r) (0x0a04 + ((r) << 3)) /* Size x */
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#define GTIDMAC_SRX_SIZE(s) (((s) - 1) & 0xffff0000)
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#define GTIDMAC_HARXR(x) (0x0a60 + ((x) << 2)) /* High Addr Remap x */
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#define GTIDMAC_BAER 0x0a80 /* Base Addr Enable */
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#define GTIDMAC_BAER_EN(w) (1 << (w))
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#define GTIDMAC_CXAPR(x) (0x0a70 + ((x) << 2)) /* Chan x Acs Protect */
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#define GTIDMAC_CXAPR_WINACC(w, ac) ((ac) << ((w) << 1))
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#define GTIDMAC_CXAPR_WINACC_NOAA 0x0 /* No access allowed */
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#define GTIDMAC_CXAPR_WINACC_RO 0x1 /* Read Only */
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#define GTIDMAC_CXAPR_WINACC_RESV 0x2 /* Reserved */
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#define GTIDMAC_CXAPR_WINACC_FA 0x3 /* Full access */
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/* XOR Engine Descriptor Registers */
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#define MVXORE_XEXNDPR(sc, x) /* Next Desc Pointer */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0b00)
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#define MVXORE_XEXCDPR(sc, x) /* Current Desc Ptr */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0b10)
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#define MVXORE_XEXBCR(sc, x) /* Byte Count */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0b20)
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/* XOR Engine Address Decording Registers */
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#define MVXORE_XEXWCR(sc, x) /* Window Control */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0b40)
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#define MVXORE_XEXWCR_WINEN(w) (1 << (w))
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#define MVXORE_XEXWCR_WINACC(w, ac) ((ac) << (((w) << 1) + 16))
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#define MVXORE_XEXWCR_WINACC_NOAA 0x0 /* No access allowed */
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#define MVXORE_XEXWCR_WINACC_RO 0x1 /* Read Only */
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#define MVXORE_XEXWCR_WINACC_RESV 0x2 /* Reserved */
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#define MVXORE_XEXWCR_WINACC_FA 0x3 /* Full access */
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#define MVXORE_XEBARX(sc, p, w) /* Base Address */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0b50 + ((w) << 2))
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#define MVXORE_XEBARX_TARGET(t) ((t) & 0xf)
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#define MVXORE_XEBARX_ATTR(a) (((a) & 0xff) << 8)
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#define MVXORE_XEBARX_BASE(b) ((b) & 0xffff0000)
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#define MVXORE_XESMRX(sc, p, w) /* Size Mask */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0b70 + ((w) << 2))
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#define MVXORE_XESMRX_SIZE(s) (((s) - 1) & 0xffff0000)
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#define MVXORE_XEHARRX(sc, p, w)/* High Address Remap */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0b90 + ((w) << 2))
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#define MVXORE_XEXAOCR(sc, x) /* Addr Override Ctrl */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0ba0)
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/* XOR Engine ECC/MemInit Registers */
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#define MVXORE_XEXDPR(sc, x) /* Destination Ptr */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0bb0)
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#define MVXORE_XEXBSR(sc, x) /* Block Size */ \
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(MVXORE_CHAN2BASE((sc), (x)) + 0x0bc0)
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#define MVXORE_XETMCR(sc, p) /* Timer Mode Control */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0bd0)
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#define MVXORE_XETMCR_TIMEREN (1 << 0)
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#define MVXORE_XETMCR_SECTIONSIZECTRL_MASK 0x1f
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#define MVXORE_XETMCR_SECTIONSIZECTRL_SHIFT 8
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#define MVXORE_XETMIVR(sc, p) /* Tmr Mode Init Val */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0bd4)
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#define MVXORE_XETMCVR(sc, p) /* Tmr Mode Curr Val */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0bd8)
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#define MVXORE_XEIVRL(sc, p) /* Initial Value Low */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0be0)
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#define MVXORE_XEIVRH(sc, p) /* Initial Value High */ \
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(MVXORE_PORT2BASE((sc), (p)) + 0x0be4)
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struct gtidmac_desc {
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#if BYTE_ORDER == LITTLE_ENDIAN
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union {
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struct {
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uint16_t rbc; /* Remind BC */
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uint16_t bcnt;
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} mode64k;
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struct {
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uint32_t bcnt;
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} mode16m;
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} bc; /* Byte Count */
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uint32_t srcaddr; /* Source Address */
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uint32_t dstaddr; /* Destination Address */
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uint32_t nextdp; /* Next Descriptor Pointer */
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#else
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uint32_t srcaddr; /* Source Address */
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union {
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struct {
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uint16_t rbc; /* Remind BC */
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uint16_t bcnt;
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} mode64k;
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struct {
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uint32_t bcnt;
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} mode16m;
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} bc; /* Byte Count */
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uint32_t nextdp; /* Next Descriptor Pointer */
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uint32_t dstaddr; /* Destination Address */
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#endif
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} __packed;
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#define GTIDMAC_DESC_BYTECOUNT_MASK 0x00ffffff
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struct mvxore_desc {
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uint32_t stat; /* Status */
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uint32_t result; /* CRC-32 Result */
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uint32_t cmd; /* Command */
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uint32_t nextda; /* Next Descriptor Address */
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uint32_t bcnt; /* Byte Count */
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uint32_t dstaddr; /* Destination Address */
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uint32_t srcaddr[MVXORE_NSRC]; /* Source Address #0-7 */
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uint32_t reserved[2];
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} __packed;
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#define MVXORE_DESC_STAT_SUCCESS (1 << 30)
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#define MVXORE_DESC_STAT_OWN (1 << 31)
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#define MVXORE_DESC_CMD_SRCCMD(s) (1 << (s))
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#define MVXORE_DESC_CMD_CRCLAST (1 << 30) /* Indicate last desc CRC32 */
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#define MVXORE_DESC_CMD_EODINTEN (1 << 31) /* End of Desc Intr Enable */
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#define MVXORE_DESC_BCNT_MASK 0x00ffffff
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#endif /* _GTIDMACREG_H_ */
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