797 lines
32 KiB
C
797 lines
32 KiB
C
/* $NetBSD: gtethreg.h,v 1.6 2021/11/10 17:19:30 msaitoh Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_GTETHREG_H_
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#define _DEV_GTETHREG_H_
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#define ETH__BIT(bit) (1U << (bit))
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#define ETH__LLBIT(bit) (1LLU << (bit))
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#define ETH__MASK(bit) (ETH__BIT(bit) - 1)
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#define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1)
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#define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len))
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#define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len))
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#define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit)))
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#define ETH__INS(new, bit) ((new) << (bit))
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#define ETH__LLINS(new, bit) ((uint64_t)(new) << (bit))
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/*
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* Descriptors used for both receive & transmit data. Note that the descriptor
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* must start on a 4LW boundary. Since the GT accesses the descriptor as
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* two 64-bit quantities, we must present them 32bit quantities in the right
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* order based on endianness.
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*/
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struct gt_eth_desc {
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#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
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u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */
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u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */
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u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */
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u_int32_t ed_bufptr; /* pointer to packet buffer */
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#endif
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#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN
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u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */
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u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */
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u_int32_t ed_bufptr; /* pointer to packet buffer */
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u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */
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#endif
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};
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/* Table 578: Ethernet TX Descriptor - Command/Status word
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* All bits except F, EI, AM, O are only valid if TX_CMD_L is also set,
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* otherwise should be 0 (tx).
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*/
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#define TX_STS_LC ETH__BIT(5) /* Late Collision */
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#define TX_STS_UR ETH__BIT(6) /* Underrun error */
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#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */
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#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */
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#define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */
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#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */
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#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
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#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
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#define TX_CMD_P ETH__BIT(18) /* Pad Packet */
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#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */
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#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
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#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */
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#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
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#define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O)
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#define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O)
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/* Table 582: Ethernet RX Descriptor - Command/Status Word
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* All bits except F, EI, AM, O are only valid if RX_CMD_L is also set,
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* otherwise should be ignored (rx).
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*/
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#define RX_STS_CE ETH__BIT(0) /* CRC Error */
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#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */
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#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */
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#define RX_STS_OR ETH__BIT(6) /* Overrun Error */
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#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */
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#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */
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#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */
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#define RX_STS_M ETH__BIT(12) /* Missed Frame */
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#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */
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#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */
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#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */
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#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
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#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
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#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
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#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */
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#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
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/* Table 586: Hash Table Entry Fields
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*/
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#define HSH_V ETH__LLBIT(0) /* Entry is valid */
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#define HSH_S ETH__LLBIT(1) /* Skip this entry */
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#define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */
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#define HSH_R ETH__LLBIT(2) /* Receive(1) */
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#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2)
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#define HSH_PRIO_INS(v) ETH__LLINS(v, 51)
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#define HSH_ADDR_MASK 0x7fffff8LLU
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#define HSH_LIMIT 12
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#define ETHC_SIZE 0x4000 /* Register Space */
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#define ETH_EPAR 0x2000 /* PHY Address Register */
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#define ETH_ESMIR 0x2010 /* SMI Register */
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#define ETH_BASE(u) (ETH0_BASE + ((u) << 10)) /* Ethernet Register Base */
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#define ETH_NUM 3
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#define ETH_SIZE 0x0400 /* Register Space */
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#define ETH_EBASE 0x0000 /* Base of Registers */
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#define ETH_EPCR 0x0000 /* Port Config. Register */
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#define ETH_EPCXR 0x0008 /* Port Config. Extend Reg */
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#define ETH_EPCMR 0x0010 /* Port Command Register */
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#define ETH_EPSR 0x0018 /* Port Status Register */
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#define ETH_ESPR 0x0020 /* Port Serial Parameters Reg */
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#define ETH_EHTPR 0x0028 /* Port Hash Table Pointer Reg*/
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#define ETH_EFCSAL 0x0030 /* Flow Control Src Addr Low */
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#define ETH_EFCSAH 0x0038 /* Flow Control Src Addr High */
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#define ETH_ESDCR 0x0040 /* SDMA Configuration Reg */
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#define ETH_ESDCMR 0x0048 /* SDMA Command Register */
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#define ETH_EICR 0x0050 /* Interrupt Cause Register */
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#define ETH_EIMR 0x0058 /* Interrupt Mask Register */
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#define ETH_EFRDP0 0x0080 /* First Rx Desc Pointer 0 */
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#define ETH_EFRDP1 0x0084 /* First Rx Desc Pointer 1 */
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#define ETH_EFRDP2 0x0088 /* First Rx Desc Pointer 2 */
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#define ETH_EFRDP3 0x008c /* First Rx Desc Pointer 3 */
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#define ETH_ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */
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#define ETH_ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */
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#define ETH_ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */
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#define ETH_ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */
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#define ETH_ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */
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#define ETH_ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */
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#define ETH_EDSCP2P0L 0x0060 /* IP Differentiated Services
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CodePoint to Priority0 low */
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#define ETH_EDSCP2P0H 0x0064 /* IP Differentiated Services
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CodePoint to Priority0 high*/
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#define ETH_EDSCP2P1L 0x0068 /* IP Differentiated Services
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CodePoint to Priority1 low */
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#define ETH_EDSCP2P1H 0x006c /* IP Differentiated Services
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CodePoint to Priority1 high*/
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#define ETH_EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */
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#define ETH_EMIBCTRS 0x0100 /* MIB Counters */
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#define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f)
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#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\
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ETH__INS(reg, 21)|\
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ETH_ESMIR_ReadOpcode)
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#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\
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ETH__INS(reg, 21)|\
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ETH__INS(val, 0)|\
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ETH_ESMIR_WriteOpcode)
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#define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16)
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#define ETH_ESMIR_WriteOpcode 0
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#define ETH_ESMIR_ReadOpcode ETH__BIT(26)
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#define ETH_ESMIR_ReadValid ETH__BIT(27)
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#define ETH_ESMIR_Busy ETH__BIT(28)
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/*
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* Table 597: Port Configuration Register (PCR)
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* 00:00 PM Promiscuous mode
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* 0: Normal mode (Frames are only received if the
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* destination address is found in the hash
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* table)
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* 1: Promiscuous mode (Frames are received
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* regardless of their destination address.
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* Errored frames are discarded unless the Port
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* Configuration register's PBF bit is set)
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* 01:01 RBM Reject Broadcast Mode
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* 0: Receive broadcast address
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* 1: Reject frames with broadcast address
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* Overridden by the promiscuous mode.
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* 02:02 PBF Pass Bad Frames
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* (0: Normal mode, 1: Pass bad Frames)
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* The Ethernet receiver passes to the CPU errored
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* frames (like fragments and collided packets)
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* that are normally rejected.
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* NOTE: Frames are only passed if they
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* successfully pass address filtering.
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* 06:03 Reserved
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* 07:07 EN Enable (0: Disabled, 1: Enable)
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* When enabled, the ethernet port is ready to
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* transmit/receive.
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* 09:08 LPBK Loop Back Mode
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* 00: Normal mode
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* 01: Internal loop back mode (TX data is looped
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* back to the RX lines. No transition is seen
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* on the interface pins)
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* 10: External loop back mode (TX data is looped
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* back to the RX lines and also transmitted
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* out to the MII interface pins)
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* 11: Reserved
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* 10:10 FC Force Collision
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* 0: Normal mode.
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* 1: Force Collision on any TX frame.
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* For RXM test (in Loopback mode).
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* 11:11 Reserved.
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* 12:12 HS Hash Size
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* 0: 8K address filtering
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* (256KB of memory space required).
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* 1: 512 address filtering
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* ( 16KB of memory space required).
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* 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1)
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* 14:14 HDM Hash Default Mode
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* 0: Discard addresses not found in address table
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* 1: Pass addresses not found in address table
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* 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex)
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* NOTE: Valid only when auto-negotiation for
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* duplex mode is disabled.
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* 30:16 Reserved
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* 31:31 ACCS Accelerate Slot Time
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* (0: Normal mode, 1: Reserved)
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*/
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#define ETH_EPCR_PM ETH__BIT(0)
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#define ETH_EPCR_RBM ETH__BIT(1)
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#define ETH_EPCR_PBF ETH__BIT(2)
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#define ETH_EPCR_EN ETH__BIT(7)
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#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2)
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#define ETH_EPCR_LPBK_Normal 0
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#define ETH_EPCR_LPBK_Internal 1
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#define ETH_EPCR_LPBK_External 2
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#define ETH_EPCR_FC ETH__BIT(10)
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#define ETH_EPCR_HS ETH__BIT(12)
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#define ETH_EPCR_HS_8K 0
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#define ETH_EPCR_HS_512 ETH_EPCR_HS
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#define ETH_EPCR_HM ETH__BIT(13)
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#define ETH_EPCR_HM_0 0
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#define ETH_EPCR_HM_1 ETH_EPCR_HM
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#define ETH_EPCR_HDM ETH__BIT(14)
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#define ETH_EPCR_HDM_Discard 0
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#define ETH_EPCR_HDM_Pass ETH_EPCR_HDM
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#define ETH_EPCR_HD_Half 0
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#define ETH_EPCR_HD_Full ETH_EPCR_HD_Full
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#define ETH_EPCR_ACCS ETH__BIT(31)
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/*
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* Table 598: Port Configuration Extend Register (PCXR)
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* 00:00 IGMP IGMP Packets Capture Enable
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* 0: IGMP packets are treated as normal Multicast
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* packets.
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* 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3
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* are trapped and sent to high priority RX
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* queue.
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* 01:01 SPAN Spanning Tree Packets Capture Enable
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* 0: BPDU (Bridge Protocol Data Unit) packets are
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* treated as normal Multicast packets.
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* 1: BPDU packets are trapped and sent to high
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* priority RX queue.
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* 02:02 PAR Partition Enable (0: Normal, 1: Partition)
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* When more than 61 collisions occur while
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* transmitting, the port enters Partition mode.
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* It waits for the first good packet from the
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* wire and then goes back to Normal mode. Under
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* Partition mode it continues transmitting, but
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* it does not receive.
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* 05:03 PRIOtx Priority weight in the round-robin between high
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* and low priority TX queues.
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* 000: 1 pkt from HIGH, 1 pkt from LOW.
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* 001: 2 pkt from HIGH, 1 pkt from LOW.
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* 010: 4 pkt from HIGH, 1 pkt from LOW.
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* 011: 6 pkt from HIGH, 1 pkt from LOW.
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* 100: 8 pkt from HIGH, 1 pkt from LOW.
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* 101: 10 pkt from HIGH, 1 pkt from LOW.
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* 110: 12 pkt from HIGH, 1 pkt from LOW.
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* 111: All pkt from HIGH, 0 pkt from LOW. LOW is
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* served only if HIGH is empty.
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* NOTE: If the HIGH queue is emptied before
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* finishing the count, the count is reset
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* until the next first HIGH comes in.
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* 07:06 PRIOrx Default Priority for Packets Received on this
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* Port (00: Lowest priority, 11: Highest priority)
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* 08:08 PRIOrx_Override Override Priority for Packets Received on this
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* Port (0: Do not override, 1: Override with
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* <PRIOrx> field)
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* 09:09 DPLXen Enable Auto-negotiation for Duplex Mode
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* (0: Enable, 1: Disable)
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* 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control
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* 0: Enable; When enabled, 1 is written (through
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* SMI access) to the PHY's register 4 bit 10
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* to advertise flow-control capability.
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* 1: Disable; Only enables flow control after the
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* PHY address is set by the CPU. When changing
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* the PHY address the flow control
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* auto-negotiation must be disabled.
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* 11:11 FLP Force Link Pass
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* (0: Force Link Pass, 1: Do NOT Force Link pass)
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* 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable)
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* NOTE: Only valid when auto negotiation for flow
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* control is disabled.
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* 13:13 Reserved
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* 15:14 MFL Max Frame Length
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* Maximum packet allowed for reception (including
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* CRC): 00: 1518 bytes, 01: 1536 bytes,
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* 10: 2048 bytes, 11: 64K bytes
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* 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect)
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* 17:17 MIBctrMode Reserved. (MBZ)
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* 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec)
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* NOTE: Only valid if SpeedEn bit is set.
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* 19:19 SpeedEn Enable Auto-negotiation for Speed
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* (0: Enable, 1: Disable)
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* 20:20 RMIIen RMII enable
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* 0: Port functions as MII port
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* 1: Port functions as RMII port
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* 21:21 DSCPen DSCP enable
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* 0: IP DSCP field decoding is disabled.
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* 1: IP DSCP field decoding is enabled.
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* 31:22 Reserved
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*/
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#define ETH_EPCXR_IGMP ETH__BIT(0)
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#define ETH_EPCXR_SPAN ETH__BIT(1)
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#define ETH_EPCXR_PAR ETH__BIT(2)
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#define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3)
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#define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3)
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#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8)
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#define ETH_EPCXR_DLPXen ETH__BIT(9)
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#define ETH_EPCXR_FCTLen ETH__BIT(10)
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#define ETH_EPCXR_FLP ETH__BIT(11)
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#define ETH_EPCXR_FCTL ETH__BIT(12)
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#define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2)
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#define ETH_EPCXR_MFL_SET(v) ((v) << 14)
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#define ETH_EPCXR_MFL_MASK 0x3
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#define ETH_EPCXR_MFL_1518 0
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#define ETH_EPCXR_MFL_1536 1
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#define ETH_EPCXR_MFL_2084 2
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#define ETH_EPCXR_MFL_64K 3
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#define ETH_EPCXR_MIBclrMode ETH__BIT(16)
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#define ETH_EPCXR_MIBctrMode ETH__BIT(17)
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#define ETH_EPCXR_Speed ETH__BIT(18)
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#define ETH_EPCXR_SpeedEn ETH__BIT(19)
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#define ETH_EPCXR_RMIIEn ETH__BIT(20)
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#define ETH_EPCXR_DSCPEn ETH__BIT(21)
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/*
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* Table 599: Port Command Register (PCMR)
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* 14:00 Reserved
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* 15:15 FJ Force Jam / Flow Control
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* When in half-duplex mode, the CPU uses this bit
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* to force collisions on the Ethernet segment.
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* When the CPU recognizes that it is going to run
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* out of receive buffers, it can force the
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* transmitter to send jam frames, forcing
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* collisions on the wire. To allow transmission
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* on the Ethernet segment, the CPU must clear the
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* FJ bit when more resources are available. When
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* in full-duplex and flow-control is enabled, this
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* bit causes the port's transmitter to send
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* flow-control PAUSE packets. The CPU must reset
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* this bit when more resources are available.
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* 31:16 Reserved
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*/
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#define ETH_EPCMR_FJ ETH__BIT(15)
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/*
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* Table 600: Port Status Register (PSR) -- Read Only
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* 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs)
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* 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full)
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|
* 02:02 Fctl Indicates Flow-control Mode
|
|
* (0: enabled, 1: disabled)
|
|
* 03:03 Link Indicates Link Status (0: down, 1: up)
|
|
* 04:04 Pause Indicates that the port is in flow-control
|
|
* disabled state. This bit is set when an IEEE
|
|
* 802.3x flow-control PAUSE (XOFF) packet is
|
|
* received (assuming that flow-control is
|
|
* enabled and the port is in full-duplex mode).
|
|
* Reset when XON is received, or when the XOFF
|
|
* timer has expired.
|
|
* 05:05 TxLow Tx Low Priority Status
|
|
* Indicates the status of the low priority
|
|
* transmit queue: (0: Stopped, 1: Running)
|
|
* 06:06 TxHigh Tx High Priority Status
|
|
* Indicates the status of the high priority
|
|
* transmit queue: (0: Stopped, 1: Running)
|
|
* 07:07 TXinProg TX in Progress
|
|
* Indicates that the port's transmitter is in an
|
|
* active transmission state.
|
|
* 31:08 Reserved
|
|
*/
|
|
#define ETH_EPSR_Speed ETH__BIT(0)
|
|
#define ETH_EPSR_Duplex ETH__BIT(1)
|
|
#define ETH_EPSR_Fctl ETH__BIT(2)
|
|
#define ETH_EPSR_Link ETH__BIT(3)
|
|
#define ETH_EPSR_Pause ETH__BIT(4)
|
|
#define ETH_EPSR_TxLow ETH__BIT(5)
|
|
#define ETH_EPSR_TxHigh ETH__BIT(6)
|
|
#define ETH_EPSR_TXinProg ETH__BIT(7)
|
|
|
|
|
|
/*
|
|
* Table 601: Serial Parameters Register (SPR)
|
|
* 01:00 JAM_LENGTH Two bits to determine the JAM Length
|
|
* (in Backpressure) as follows:
|
|
* 00 = 12K bit-times
|
|
* 01 = 24K bit-times
|
|
* 10 = 32K bit-times
|
|
* 11 = 48K bit-times
|
|
* 06:02 JAM_IPG Five bits to determine the JAM IPG.
|
|
* The step is four bit-times. The value may vary
|
|
* between 4 bit time to 124.
|
|
* 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA.
|
|
* The step is four bit-times. The value may vary
|
|
* between 4 bit time to 124.
|
|
* 16:12 IPG_DATA Inter-Packet Gap (IPG)
|
|
* The step is four bit-times. The value may vary
|
|
* between 12 bit time to 124.
|
|
* NOTE: These bits may be changed only when the
|
|
* Ethernet ports is disabled.
|
|
* 21:17 Data_Blind Data Blinder
|
|
* The number of nibbles from the beginning of the
|
|
* IPG, in which the IPG counter is restarted when
|
|
* detecting a carrier activity. Following this
|
|
* value, the port enters the Data Blinder zone and
|
|
* does not reset the IPG counter. This ensures
|
|
* fair access to the medium.
|
|
* The default is 10 hex (64 bit times - 2/3 of the
|
|
* default IPG). The step is 4 bit-times. Valid
|
|
* range is 3 to 1F hex nibbles.
|
|
* NOTE: These bits may be only changed when the
|
|
* Ethernet port is disabled.
|
|
* 22:22 Limit4 The number of consecutive packet collisions that
|
|
* occur before the collision counter is reset.
|
|
* 0: The port resets its collision counter after
|
|
* 16 consecutive retransmit trials and
|
|
* restarts the Backoff algorithm.
|
|
* 1: The port resets its collision counter and
|
|
* restarts the Backoff algorithm after 4
|
|
* consecutive transmit trials.
|
|
* 31:23 Reserved
|
|
*/
|
|
#define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2)
|
|
#define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5)
|
|
#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5)
|
|
#define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5)
|
|
#define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5)
|
|
#define ETH_ESPR_Limit4(v) ETH__BIT(22)
|
|
|
|
/*
|
|
* Table 602: Hash Table Pointer Register (HTPR)
|
|
* 31:00 HTP 32-bit pointer to the address table.
|
|
* Bits [2:0] must be set to zero.
|
|
*/
|
|
|
|
/*
|
|
* Table 603: Flow Control Source Address Low (FCSAL)
|
|
* 15:0 SA[15:0] Source Address
|
|
* The least significant bits of the source
|
|
* address for the port. This address is used for
|
|
* Flow Control.
|
|
* 31:16 Reserved
|
|
*/
|
|
|
|
/*
|
|
* Table 604: Flow Control Source Address High (FCSAH)
|
|
* 31:0 SA[47:16] Source Address
|
|
* The most significant bits of the source address
|
|
* for the port. This address is used for Flow
|
|
* Control.
|
|
*/
|
|
|
|
|
|
/*
|
|
* Table 605: SDMA Configuration Register (SDCR)
|
|
* 01:00 Reserved
|
|
* 05:02 RC Retransmit Count
|
|
* Sets the maximum number of retransmits per
|
|
* packet. After executing retransmit for RC
|
|
* times, the TX SDMA closes the descriptor with a
|
|
* Retransmit Limit error indication and processes
|
|
* the next packet. When RC is set to 0, the
|
|
* number of retransmits is unlimited. In this
|
|
* case, the retransmit process is only terminated
|
|
* if CPU issues an Abort command.
|
|
* 06:06 BLMR Big/Little Endian Receive Mode
|
|
* The DMA supports Big or Little Endian
|
|
* configurations on a per channel basis. The BLMR
|
|
* bit only affects data transfer to memory.
|
|
* 0: Big Endian
|
|
* 1: Little Endian
|
|
* 07:07 BLMT Big/Little Endian Transmit Mode
|
|
* The DMA supports Big or Little Endian
|
|
* configurations on a per channel basis. The BLMT
|
|
* bit only affects data transfer from memory.
|
|
* 0: Big Endian
|
|
* 1: Little Endian
|
|
* 08:08 POVR PCI Override
|
|
* When set, causes the SDMA to direct all its
|
|
* accesses in PCI_0 direction and overrides
|
|
* normal address decoding process.
|
|
* 09:09 RIFB Receive Interrupt on Frame Boundaries
|
|
* When set, the SDMA Rx generates interrupts only
|
|
* on frame boundaries (i.e. after writing the
|
|
* frame status to the descriptor).
|
|
* 11:10 Reserved
|
|
* 13:12 BSZ Burst Size
|
|
* Sets the maximum burst size for SDMA
|
|
* transactions:
|
|
* 00: Burst is limited to 1 64bit words.
|
|
* 01: Burst is limited to 2 64bit words.
|
|
* 10: Burst is limited to 4 64bit words.
|
|
* 11: Burst is limited to 8 64bit words.
|
|
* 31:14 Reserved
|
|
*/
|
|
#define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4)
|
|
#define ETH_ESDCR_BLMR ETH__BIT(6)
|
|
#define ETH_ESDCR_BLMT ETH__BIT(7)
|
|
#define ETH_ESDCR_POVR ETH__BIT(8)
|
|
#define ETH_ESDCR_RIFB ETH__BIT(9)
|
|
#define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2)
|
|
#define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\
|
|
(v) |= ETH__INS(n, 12))
|
|
#define ETH_ESDCR_BSZ_1 0
|
|
#define ETH_ESDCR_BSZ_2 1
|
|
#define ETH_ESDCR_BSZ_4 2
|
|
#define ETH_ESDCR_BSZ_8 3
|
|
|
|
#define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \
|
|
"4 64-bit words", "8 64-bit words" }
|
|
|
|
/*
|
|
* Table 606: SDMA Command Register (SDCMR)
|
|
* 06:00 Reserved
|
|
* 07:07 ERD Enable RX DMA.
|
|
* Set to 1 by the CPU to cause the SDMA to start
|
|
* a receive process. Cleared when the CPU issues
|
|
* an Abort Receive command.
|
|
* 14:08 Reserved
|
|
* 15:15 AR Abort Receive
|
|
* Set to 1 by the CPU to abort a receive SDMA
|
|
* operation. When the AR bit is set, the SDMA
|
|
* aborts its current operation and moves to IDLE.
|
|
* No descriptor is closed. The AR bit is cleared
|
|
* upon entering IDLE. After setting the AR bit,
|
|
* the CPU must poll the bit to verify that the
|
|
* abort sequence is completed.
|
|
* 16:16 STDH Stop TX High
|
|
* Set to 1 by the CPU to stop the transmission
|
|
* process from the high priority queue at the end
|
|
* of the current frame. An interrupt is generated
|
|
* when the stop command has been executed.
|
|
* Writing 1 to STDH resets TXDH bit.
|
|
* Writing 0 to this bit has no effect.
|
|
* 17:17 STDL Stop TX Low
|
|
* Set to 1 by the CPU to stop the transmission
|
|
* process from the low priority queue at the end
|
|
* of the current frame. An interrupt is generated
|
|
* when the stop command has been executed.
|
|
* Writing 1 to STDL resets TXDL bit.
|
|
* Writing 0 to this bit has no effect.
|
|
* 22:18 Reserved
|
|
* 23:23 TXDH Start Tx High
|
|
* Set to 1 by the CPU to cause the SDMA to fetch
|
|
* the first descriptor and start a transmit
|
|
* process from the high priority Tx queue.
|
|
* Writing 1 to TXDH resets STDH bit.
|
|
* Writing 0 to this bit has no effect.
|
|
* 24:24 TXDL Start Tx Low
|
|
* Set to 1 by the CPU to cause the SDMA to fetch
|
|
* the first descriptor and start a transmit
|
|
* process from the low priority Tx queue.
|
|
* Writing 1 to TXDL resets STDL bit.
|
|
* Writing 0 to this bit has no effect.
|
|
* 30:25 Reserved
|
|
* 31:31 AT Abort Transmit
|
|
* Set to 1 by the CPU to abort a transmit DMA
|
|
* operation. When the AT bit is set, the SDMA
|
|
* aborts its current operation and moves to IDLE.
|
|
* No descriptor is closed. Cleared upon entering
|
|
* IDLE. After setting AT bit, the CPU must poll
|
|
* it in order to verify that the abort sequence
|
|
* is completed.
|
|
*/
|
|
#define ETH_ESDCMR_ERD ETH__BIT(7)
|
|
#define ETH_ESDCMR_AR ETH__BIT(15)
|
|
#define ETH_ESDCMR_STDH ETH__BIT(16)
|
|
#define ETH_ESDCMR_STDL ETH__BIT(17)
|
|
#define ETH_ESDCMR_TXDH ETH__BIT(23)
|
|
#define ETH_ESDCMR_TXDL ETH__BIT(24)
|
|
#define ETH_ESDCMR_AT ETH__BIT(31)
|
|
|
|
/*
|
|
* Table 607: Interrupt Cause Register (ICR)
|
|
* 00:00 RxBuffer Rx Buffer Return
|
|
* Indicates an Rx buffer returned to CPU ownership
|
|
* or that the port finished reception of a Rx
|
|
* frame in either priority queues.
|
|
* NOTE: In order to get a Rx Buffer return per
|
|
* priority queue, use bit 19:16. This bit is
|
|
* set upon closing any Rx descriptor which
|
|
* has its EI bit set. To limit the
|
|
* interrupts to frame (rather than buffer)
|
|
* boundaries, the user must set SDMA
|
|
* Configuration register's RIFB bit. When
|
|
* the RIFB bit is set, an interrupt
|
|
* generates only upon closing the first
|
|
* descriptor of a received packet, if this
|
|
* descriptor has it EI bit set.
|
|
* 01:01 Reserved
|
|
* 02:02 TxBufferHigh Tx Buffer for High priority Queue
|
|
* Indicates a Tx buffer returned to CPU ownership
|
|
* or that the port finished transmission of a Tx
|
|
* frame.
|
|
* NOTE: This bit is set upon closing any Tx
|
|
* descriptor which has its EI bit set. To
|
|
* limit the interrupts to frame (rather than
|
|
* buffer) boundaries, the user must set EI
|
|
* only in the last descriptor.
|
|
* 03:03 TxBufferLow Tx Buffer for Low Priority Queue
|
|
* Indicates a Tx buffer returned to CPU ownership
|
|
* or that the port finished transmission of a Tx
|
|
* frame.
|
|
* NOTE: This bit is set upon closing any Tx
|
|
* descriptor which has its EI bit set. To
|
|
* limit the interrupts to frame (rather than
|
|
* buffer) boundaries, the user must set EI
|
|
* only in the last descriptor.
|
|
* 05:04 Reserved
|
|
* 06:06 TxEndHigh Tx End for High Priority Queue
|
|
* Indicates that the Tx DMA stopped processing the
|
|
* high priority queue after stop command, or that
|
|
* it reached the end of the high priority
|
|
* descriptor chain.
|
|
* 07:07 TxEndLow Tx End for Low Priority Queue
|
|
* Indicates that the Tx DMA stopped processing the
|
|
* low priority queue after stop command, or that
|
|
* it reached the end of the low priority
|
|
* descriptor chain.
|
|
* 08:08 RxError Rx Resource Error
|
|
* Indicates a Rx resource error event in one of
|
|
* the priority queues.
|
|
* NOTE: To get a Rx Resource Error Indication per
|
|
* priority queue, use bit 23:20.
|
|
* 09:09 Reserved
|
|
* 10:10 TxErrorHigh Tx Resource Error for High Priority Queue
|
|
* Indicates a Tx resource error event during
|
|
* packet transmission from the high priority queue
|
|
* 11:11 TxErrorLow Tx Resource Error for Low Priority Queue
|
|
* Indicates a Tx resource error event during
|
|
* packet transmission from the low priority queue
|
|
* 12:12 RxOVR Rx Overrun
|
|
* Indicates an overrun event that occurred during
|
|
* reception of a packet.
|
|
* 13:13 TxUdr Tx Underrun
|
|
* Indicates an underrun event that occurred during
|
|
* transmission of packet from either queue.
|
|
* 15:14 Reserved
|
|
* 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0]
|
|
* Indicates a Rx buffer returned to CPU ownership
|
|
* or that the port completed reception of a Rx
|
|
* frame in a receive priority queue[0]
|
|
* 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1]
|
|
* Indicates a Rx buffer returned to CPU ownership
|
|
* or that the port completed reception of a Rx
|
|
* frame in a receive priority queue[1].
|
|
* 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2]
|
|
* Indicates a Rx buffer returned to CPU ownership
|
|
* or that the port completed reception of a Rx
|
|
* frame in a receive priority queue[2].
|
|
* 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3]
|
|
* Indicates a Rx buffer returned to CPU ownership
|
|
* or that the port completed reception of a Rx
|
|
* frame in a receive priority queue[3].
|
|
* 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0]
|
|
* Indicates a Rx resource error event in receive
|
|
* priority queue[0].
|
|
* 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1]
|
|
* Indicates a Rx resource error event in receive
|
|
* priority queue[1].
|
|
* 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2]
|
|
* Indicates a Rx resource error event in receive
|
|
* priority queue[2].
|
|
* 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3]
|
|
* Indicates a Rx resource error event in receive
|
|
* priority queue[3].
|
|
* 27:24 Reserved
|
|
* 28:29 MIIPhySTC MII PHY Status Change
|
|
* Indicates a status change reported by the PHY
|
|
* connected to this port. Set when the MII
|
|
* management interface block identifies a change
|
|
* in PHY's register 1.
|
|
* 29:29 SMIdone SMI Command Done
|
|
* Indicates that the SMI completed a MII
|
|
* management command (either read or write) that
|
|
* was initiated by the CPU writing to the SMI
|
|
* register.
|
|
* 30:30 Reserved
|
|
* 31:31 EtherIntSum Ethernet Interrupt Summary
|
|
* This bit is a logical OR of the (unmasked) bits
|
|
* [30:04] in the Interrupt Cause register.
|
|
*/
|
|
|
|
#define ETH_IR_RxBuffer ETH__BIT(0)
|
|
#define ETH_IR_TxBufferHigh ETH__BIT(2)
|
|
#define ETH_IR_TxBufferLow ETH__BIT(3)
|
|
#define ETH_IR_TxEndHigh ETH__BIT(6)
|
|
#define ETH_IR_TxEndLow ETH__BIT(7)
|
|
#define ETH_IR_RxError ETH__BIT(8)
|
|
#define ETH_IR_TxErrorHigh ETH__BIT(10)
|
|
#define ETH_IR_TxErrorLow ETH__BIT(11)
|
|
#define ETH_IR_RxOVR ETH__BIT(12)
|
|
#define ETH_IR_TxUdr ETH__BIT(13)
|
|
#define ETH_IR_RxBuffer_0 ETH__BIT(16)
|
|
#define ETH_IR_RxBuffer_1 ETH__BIT(17)
|
|
#define ETH_IR_RxBuffer_2 ETH__BIT(18)
|
|
#define ETH_IR_RxBuffer_3 ETH__BIT(19)
|
|
#define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4)
|
|
#define ETH_IR_RxError_0 ETH__BIT(20)
|
|
#define ETH_IR_RxError_1 ETH__BIT(21)
|
|
#define ETH_IR_RxError_2 ETH__BIT(22)
|
|
#define ETH_IR_RxError_3 ETH__BIT(23)
|
|
#define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4)
|
|
#define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\
|
|
ETH_IR_RxBuffer_1|\
|
|
ETH_IR_RxBuffer_2|\
|
|
ETH_IR_RxBuffer_3|\
|
|
ETH_IR_RxError_0|\
|
|
ETH_IR_RxError_1|\
|
|
ETH_IR_RxError_2|\
|
|
ETH_IR_RxError_3)
|
|
#define ETH_IR_MIIPhySTC ETH__BIT(28)
|
|
#define ETH_IR_SMIdone ETH__BIT(29)
|
|
#define ETH_IR_EtherIntSum ETH__BIT(31)
|
|
#define ETH_IR_Summary ETH__BIT(31)
|
|
|
|
/*
|
|
* Table 608: Interrupt Mask Register (IMR)
|
|
* 31:00 Various Mask bits for the Interrupt Cause register.
|
|
*/
|
|
|
|
/*
|
|
* Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L),
|
|
* 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries.
|
|
*/
|
|
|
|
/*
|
|
* Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H)
|
|
* 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries.
|
|
*/
|
|
|
|
/*
|
|
* Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L)
|
|
* 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries.
|
|
*/
|
|
|
|
/*
|
|
* Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H)
|
|
* 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries.
|
|
*/
|
|
|
|
/*
|
|
* Table 613: VLAN Priority Tag to Priority (VPT2P)
|
|
* 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0]
|
|
* entries.
|
|
* 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0]
|
|
* entries.
|
|
* 31:16 Reserved
|
|
*/
|
|
#endif /* _DEV_GTETHREG_H_ */
|