104 lines
3.9 KiB
C
104 lines
3.9 KiB
C
/* $NetBSD: wired_map.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
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/*-
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* Copyright (c) 2005 Tadpole Computer Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Tadpole Computer Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Tadpole Computer Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_WIRED_MAP_H
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#define _MIPS_WIRED_MAP_H
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/*
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* Certain machines have peripheral busses which are only accessible
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* using the TLB.
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*
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* For example, certain Alchemy parts place PCI and PCMCIA busses at
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* physical address spaces which are beyond the normal 32-bit range.
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* In order to access these spaces TLB entries mapping 36-bit physical
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* addresses to 32-bit logical addresses must be used.
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*
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* Note that all wired mappings are must be 32 MB aligned. This is
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* because we use 32 MB mappings in the TLB. Changing this might get
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* us more effficent use of the address space, but it would greatly
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* complicate the code, and would also probably consume additional TLB
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* entries.
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*
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* Note that within a single 32 MB region, you can have multiple
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* decoders, but they must decode uniquely within the same 32MB of
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* physical address space.
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*
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* BEWARE: The start of KSEG2 (0xC0000000) is used by the NetBSD kernel
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* for context switching and is associated with wired entry 0. So you
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* cannot use that, as I discovered the hard way.
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*
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* Note also that at the moment this is not supported on the MIPS-I
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* ISA (but it shouldn't need it anyway.)
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*/
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#ifndef MIPS3_WIRED_SIZE
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#define MIPS3_WIRED_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M)
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#endif
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#define MIPS3_WIRED_OFFMASK (MIPS3_WIRED_SIZE - 1)
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#define MIPS3_WIRED_ENTRY_SIZE(pgsize) ((pgsize) * 2)
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#define MIPS3_WIRED_ENTRY_OFFMASK(pgsize) (MIPS3_WIRED_ENTRY_SIZE(pgsize) - 1)
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/*
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* This defines the maximum number of wired TLB entries that the wired
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* map will be allowed to consume. It can (and probably will!)
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* consume fewer, but it will not consume more. Note that NetBSD also
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* uses one wired entry for context switching (see TLB_WIRED_UPAGES),
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* and that is not included in this number.
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*/
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#ifndef MIPS3_NWIRED_ENTRY
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#define MIPS3_NWIRED_ENTRY 8 /* upper limit */
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#endif
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struct wired_map_entry {
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paddr_t pa0;
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paddr_t pa1;
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vaddr_t va;
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vsize_t pgmask;
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};
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extern struct wired_map_entry mips3_wired_map[];
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extern int mips3_nwired_page;
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/*
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* Wire down a region of the specified size.
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*/
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bool mips3_wired_enter_region(vaddr_t, paddr_t, vsize_t);
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/*
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* Wire down a single page using specified page size.
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*/
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bool mips3_wired_enter_page(vaddr_t, paddr_t, vsize_t);
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#endif /* _MIPS_WIRED_MAP_H */
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