429 lines
12 KiB
C
429 lines
12 KiB
C
/* $NetBSD: mips_opcode.h,v 1.26 2021/04/05 07:28:19 simonb Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93
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*/
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#ifndef _MIPS_MIPS_OPCODE_H_
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#define _MIPS_MIPS_OPCODE_H_
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/*
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* Define the instruction formats and opcode values for the
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* MIPS instruction set.
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*/
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/*
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* Define the instruction formats.
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*/
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typedef union {
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unsigned word;
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#if BYTE_ORDER == LITTLE_ENDIAN
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struct {
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unsigned imm: 16;
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unsigned rt: 5;
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unsigned rs: 5;
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unsigned op: 6;
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} IType;
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struct {
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unsigned target: 26;
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unsigned op: 6;
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} JType;
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struct {
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unsigned func: 6;
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unsigned shamt: 5;
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unsigned rd: 5;
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unsigned rt: 5;
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unsigned rs: 5;
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unsigned op: 6;
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} RType;
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struct {
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unsigned func: 6;
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unsigned fd: 5;
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unsigned fs: 5;
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unsigned ft: 5;
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unsigned fmt: 4;
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unsigned : 1; /* always '1' */
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unsigned op: 6; /* always '0x11' */
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} FRType;
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struct {
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unsigned func: 6;
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unsigned zero: 1; /* always '0' */
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unsigned offset: 9;
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unsigned rt: 5;
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unsigned rs: 5;
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unsigned op: 6;
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} S3OType; /* has "special3 offset" type */
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#endif
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#if BYTE_ORDER == BIG_ENDIAN
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struct {
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unsigned op: 6;
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unsigned rs: 5;
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unsigned rt: 5;
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unsigned imm: 16;
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} IType;
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struct {
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unsigned op: 6;
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unsigned target: 26;
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} JType;
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struct {
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unsigned op: 6;
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unsigned rs: 5;
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unsigned rt: 5;
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unsigned rd: 5;
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unsigned shamt: 5;
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unsigned func: 6;
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} RType;
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struct {
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unsigned op: 6; /* always '0x11' */
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unsigned : 1; /* always '1' */
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unsigned fmt: 4;
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unsigned ft: 5;
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unsigned fs: 5;
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unsigned fd: 5;
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unsigned func: 6;
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} FRType;
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struct {
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unsigned op: 6;
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unsigned rs: 5;
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unsigned rt: 5;
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unsigned offset: 9;
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unsigned zero: 1; /* always '0' */
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unsigned func: 6;
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} S3OType; /* has "special3 offset" type */
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#endif
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} InstFmt;
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/*
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* Values for the 'op' field.
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*/
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#define OP_SPECIAL 000
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#define OP_REGIMM 001
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#define OP_J 002
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#define OP_JAL 003
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#define OP_BEQ 004
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#define OP_BNE 005
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#define OP_BLEZ 006
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#define OP_BGTZ 007
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#define OP_ADDI 010
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#define OP_ADDIU 011
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#define OP_SLTI 012
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#define OP_SLTIU 013
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#define OP_ANDI 014
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#define OP_ORI 015
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#define OP_XORI 016
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#define OP_LUI 017
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#define OP_COP0 020
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#define OP_COP1 021
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#define OP_COP2 022
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#define OP_COP3 023
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#define OP_BEQL 024 /* MIPS-II, for r4000 port */
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#define OP_BNEL 025 /* MIPS-II, for r4000 port */
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#define OP_BLEZL 026 /* MIPS-II, for r4000 port */
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#define OP_BGTZL 027 /* MIPS-II, for r4000 port */
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#define OP_DADDI 030 /* MIPS-II, for r4000 port */
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#define OP_DADDIU 031 /* MIPS-II, for r4000 port */
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#define OP_LDL 032 /* MIPS-II, for r4000 port */
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#define OP_LDR 033 /* MIPS-II, for r4000 port */
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#define OP_SPECIAL2 034 /* QED and MIPS32/MIPS64 opcodes */
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#define OP_JALX 035
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#define OP_MDMX 036
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#define OP_SPECIAL3 037
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#define OP_LB 040
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#define OP_LH 041
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#define OP_LWL 042
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#define OP_LW 043
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#define OP_LBU 044
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#define OP_LHU 045
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#define OP_LWR 046
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#define OP_LHU 045
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#define OP_LWR 046
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#define OP_LWU 047 /* MIPS-II, for r4000 port */
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#define OP_SB 050
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#define OP_SH 051
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#define OP_SWL 052
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#define OP_SW 053
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#define OP_SDL 054 /* MIPS-II, for r4000 port */
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#define OP_SDR 055 /* MIPS-II, for r4000 port */
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#define OP_SWR 056
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#define OP_CACHE 057 /* MIPS-II, for r4000 port */
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#define OP_LL 060
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#define OP_LWC0 OP_LL /* backwards source compatibility */
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#define OP_LWC1 061
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#define OP_LWC2 062
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#define OP_PREF 063
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#define OP_LLD 064 /* MIPS-II, for r4000 port */
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#define OP_LDC1 065
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#define OP_LDC2 066
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#define OP_LD 067 /* MIPS-II, for r4000 port */
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#define OP_CVM_BBIT0 OP_LWC2
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#define OP_CVM_BBIT032 OP_LDC2
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#define OP_SC 070
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#define OP_SWC0 OP_SC /* backwards source compatibility */
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#define OP_SWC1 071
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#define OP_SWC2 072
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#define OP_RSVD073 073
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#define OP_SCD 074 /* MIPS-II, for r4000 port */
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#define OP_SDC1 075
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#define OP_SDC2 076
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#define OP_SD 077 /* MIPS-II, for r4000 port */
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#define OP_CVM_BBIT1 OP_SWC2
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#define OP_CVM_BBIT132 OP_SDC2
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/*
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* Values for the 'func' field when 'op' == OP_SPECIAL.
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*/
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#define OP_SLL 000
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#define OP_SRL 002
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#define OP_SRA 003
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#define OP_SLLV 004
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#define OP_SRLV 006
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#define OP_SRAV 007
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#define OP_JR 010
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#define OP_JALR 011
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#define OP_SYSCALL 014
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#define OP_BREAK 015
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#define OP_SYNC 017 /* MIPS-II, for r4000 port */
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#define SYNC_CVM_IODBDMA 0x02
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#define SYNC_WMB 0x04
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#define SYNC_CVM_W SYNC_WMB
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#define SYNC_CVM_WS 0x05
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#define SYNC_CVM_S 0x06
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#define SYNC_MB 0x10
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#define SYNC_ACQUIRE 0x11
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#define SYNC_RELEASE 0x12
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#define SYNC_RMB 0x13
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#define OP_MFHI 020
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#define OP_MTHI 021
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#define OP_MFLO 022
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#define OP_MTLO 023
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#define OP_DSLLV 024 /* MIPS-II, for r4000 port */
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#define OP_DSRLV 026 /* MIPS-II, for r4000 port */
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#define OP_DSRAV 027 /* MIPS-II, for r4000 port */
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#define OP_MULT 030
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#define OP_MULTU 031
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#define OP_DIV 032
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#define OP_DIVU 033
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#define OP_DMULT 034 /* MIPS-II, for r4000 port */
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#define OP_DMULTU 035 /* MIPS-II, for r4000 port */
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#define OP_DDIV 036 /* MIPS-II, for r4000 port */
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#define OP_DDIVU 037 /* MIPS-II, for r4000 port */
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#define OP_ADD 040
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#define OP_ADDU 041
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#define OP_SUB 042
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#define OP_SUBU 043
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#define OP_AND 044
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#define OP_OR 045
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#define OP_XOR 046
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#define OP_NOR 047
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#define OP_SLT 052
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#define OP_SLTU 053
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#define OP_DADD 054 /* MIPS-II, for r4000 port */
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#define OP_DADDU 055 /* MIPS-II, for r4000 port */
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#define OP_DSUB 056 /* MIPS-II, for r4000 port */
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#define OP_DSUBU 057 /* MIPS-II, for r4000 port */
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#define OP_TGE 060 /* MIPS-II, for r4000 port */
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#define OP_TGEU 061 /* MIPS-II, for r4000 port */
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#define OP_TLT 062 /* MIPS-II, for r4000 port */
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#define OP_TLTU 063 /* MIPS-II, for r4000 port */
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#define OP_TEQ 064 /* MIPS-II, for r4000 port */
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#define OP_TNE 066 /* MIPS-II, for r4000 port */
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#define OP_DSLL 070 /* MIPS-II, for r4000 port */
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#define OP_DSRL 072 /* MIPS-II, for r4000 port */
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#define OP_DSRA 073 /* MIPS-II, for r4000 port */
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#define OP_DSLL32 074 /* MIPS-II, for r4000 port */
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#define OP_DSRL32 076 /* MIPS-II, for r4000 port */
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#define OP_DSRA32 077 /* MIPS-II, for r4000 port */
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/*
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* Subvalues for SLL where the source and destination registers
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* are both zero.
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*/
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#define OP_SLL_NOP 0
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#define OP_SLL_SSNOP 1
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#define OP_SLL_EHB 3
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#define OP_SLL_PAUSE 5
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/*
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* Values for the 'func' field when 'op' == OP_SPECIAL2.
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*/
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#define OP_MADD 000 /* QED, MIPS32/64 */
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#define OP_MADDU 001 /* QED, MIPS32/64 */
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#define OP_MUL 002 /* QED, MIPS32/64 */
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#define OP_CVM_DMUL 003 /* OCTEON */
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#define OP_MSUB 004 /* MIPS32/64 */
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#define OP_MSUBU 005 /* MIPS32/64 */
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#define OP_CVM_SAA 030 /* OCTEON */
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#define OP_CVM_SAAD 031 /* OCTEON */
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#define OP_CLZ 040 /* MIPS32/64 */
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#define OP_CLO 041 /* MIPS32/64 */
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#define OP_DCLZ 044 /* MIPS32/64 */
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#define OP_DCLO 045 /* MIPS32/64 */
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#define OP_CVM_BADDU 050 /* OCTEON */
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#define OP_CVM_SEQ 052 /* OCTEON */
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#define OP_CVM_SNE 053 /* OCTEON */
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#define OP_CVM_SEQI 056 /* OCTEON */
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#define OP_CVM_SNEI 057 /* OCTEON */
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#define OP_CVM_POP 054 /* OCTEON */
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#define OP_CVM_DPOP 055 /* OCTEON */
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#define OP_CVM_CINS 062 /* OCTEON */
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#define OP_CVM_CINS32 063 /* OCTEON */
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#define OP_CVM_EXTS 072 /* OCTEON */
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#define OP_CVM_EXTS32 073 /* OCTEON */
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#define OP_SDBBP 077 /* MIPS32/MIPS64 */
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/*
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* Values for the 'func' field when 'op' == OP_SPECIAL3.
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*/
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#define OP_EXT 000 /* MIPS32/64 r2 */
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#define OP_DEXTM 001 /* MIPS32/64 r2 */
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#define OP_DEXTU 002 /* MIPS32/64 r2 */
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#define OP_DEXT 003 /* MIPS32/64 r2 */
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#define OP_INS 004 /* MIPS32/64 r2 */
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#define OP_DINSM 005 /* MIPS32/64 r2 */
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#define OP_DINSU 006 /* MIPS32/64 r2 */
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#define OP_DINS 007 /* MIPS32/64 r2 */
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#define OP_LX 012 /* DSP */
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#define OP_LWLE 031 /* EVA */
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#define OP_LWRE 032 /* EVA */
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#define OP_CACHEE 033 /* EVA */
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#define OP_SBE 034 /* EVA */
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#define OP_SHE 035 /* EVA */
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#define OP_SCE 036 /* EVA */
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#define OP_SWE 037 /* EVA */
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#define OP_BSHFL 040 /* MIPS32/64 r2 */
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#define OP_SWLE 041 /* EVA */
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#define OP_SWRE 042 /* EVA */
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#define OP_PREFE 043 /* EVA */
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#define OP_DBSHFL 044 /* MIPS32/64 r2 */
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#define OP_CACHE_R6 045 /* MIPS32/64 r6 */
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#define OP_LBUE 050 /* EVA */
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#define OP_LHUE 051 /* EVA */
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#define OP_LBE 054 /* EVA */
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#define OP_LHE 055 /* EVA */
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#define OP_LLE 056 /* EVA */
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#define OP_LWE 057 /* EVA */
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#define OP_RDHWR 073 /* MIPS32/64 r2 */
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#define OP_BSHFL_SBH 002 /* swap bytes within halfwords */
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#define OP_BSHFL_SHD 005 /* swap halfworks within double */
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#define OP_BSHFL_SEB 020 /* sign extend byte */
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#define OP_BSHFL_SEH 030 /* sign extend halfword */
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#define OP_LX_LWX 0 /* lwx */
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#define OP_LX_LHX 4 /* lhx */
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#define OP_LX_LBUX 6 /* lbux */
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#define OP_LX_LDX 8 /* ldx */
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/*
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* Values for the 'func' field when 'op' == OP_REGIMM.
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*/
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#define OP_BLTZ 000
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#define OP_BGEZ 001
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#define OP_BLTZL 002 /* MIPS-II, for r4000 port */
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#define OP_BGEZL 003 /* MIPS-II, for r4000 port */
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#define OP_TGEI 010 /* MIPS-II, for r4000 port */
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#define OP_TGEIU 011 /* MIPS-II, for r4000 port */
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#define OP_TLTI 012 /* MIPS-II, for r4000 port */
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#define OP_TLTIU 013 /* MIPS-II, for r4000 port */
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#define OP_TEQI 014 /* MIPS-II, for r4000 port */
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#define OP_TNEI 016 /* MIPS-II, for r4000 port */
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#define OP_BLTZAL 020 /* MIPS-II, for r4000 port */
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#define OP_BGEZAL 021
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#define OP_BLTZALL 022
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#define OP_BGEZALL 023
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/*
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* Values for the 'rs' field when 'op' == OP_COPz.
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*/
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#define OP_MF 000
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#define OP_DMF 001 /* MIPS-II, for r4000 port */
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#define OP_CF 002
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#define OP_MFH 003
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#define OP_MT 004
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#define OP_DMT 005 /* MIPS-II, for r4000 port */
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#define OP_CT 006
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#define OP_MTH 007
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#define OP_BCx 010
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#define OP_MFM 013 /* MIPS32/64 r2 */
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#define OP_BCy 014
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/*
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* Values for the 'rt' field when 'op' == OP_COPz.
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*/
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#define COPz_BC_TF_MASK 0x01
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#define COPz_BC_TRUE 0x01
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#define COPz_BC_FALSE 0x00
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#define COPz_BCL_TF_MASK 0x02 /* MIPS-II, for r4000 port */
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#define COPz_BCL_TRUE 0x02 /* MIPS-II, for r4000 port */
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#define COPz_BCL_FALSE 0x00 /* MIPS-II, for r4000 port */
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#define INSN_LUI_P(insn) (((insn) >> 26) == OP_LUI)
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#define INSN_LW_P(insn) (((insn) >> 26) == OP_LW)
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#define INSN_SW_P(insn) (((insn) >> 26) == OP_SW)
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#define INSN_LD_P(insn) (((insn) >> 26) == OP_LD)
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#define INSN_SD_P(insn) (((insn) >> 26) == OP_SD)
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#define INSN_LOAD_P(insn) (INSN_LD_P(insn) || INSN_LW_P(insn))
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#define INSN_STORE_P(insn) (INSN_SD_P(insn) || INSN_SW_P(insn))
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#endif /* _MIPS_MIPS_OPCODE_H_ */
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