165 lines
4.8 KiB
C
165 lines
4.8 KiB
C
/* $NetBSD: intr.h,v 1.13 2021/02/16 05:11:26 simonb Exp $ */
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/*-
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* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_INTR_H_
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#define _MIPS_INTR_H_
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#ifdef _KERNEL_OPT
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#include "opt_multiprocessor.h"
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#endif
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/*
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* This is a common <machine/intr.h> for all MIPS platforms.
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*/
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#define IPL_NONE 0
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#define IPL_SOFTCLOCK (IPL_NONE+1)
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#define IPL_SOFTBIO (IPL_SOFTCLOCK) /* shares SWINT with softclock */
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#define IPL_SOFTNET (IPL_SOFTBIO+1)
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#define IPL_SOFTSERIAL (IPL_SOFTNET) /* shares SWINT with softnet */
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#define IPL_VM (IPL_SOFTSERIAL+1)
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#define IPL_SCHED (IPL_VM+1)
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#define IPL_DDB (IPL_SCHED+1)
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#define IPL_HIGH (IPL_DDB+1)
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#define IPL_SAFEPRI IPL_SOFTSERIAL
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#define _IPL_N (IPL_HIGH+1)
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#define _IPL_NAMES(pfx) { pfx"none", pfx"softclock/bio", pfx"softnet/serial", \
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pfx"vm", pfx"sched", pfx"ddb", pfx"high" }
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#define IST_UNUSABLE -1 /* interrupt cannot be used */
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#define IST_NONE 0 /* none (dummy) */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#define IST_LEVEL_HIGH 4 /* level triggered, active high */
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#define IST_LEVEL_LOW 5 /* level triggered, active low */
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#define IST_MPSAFE 0x100 /* interrupt is MPSAFE */
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#define IPI_NOP 0 /* do nothing, interrupt only */
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#define IPI_AST 1 /* force ast */
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#define IPI_SHOOTDOWN 2 /* do a tlb shootdown */
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#define IPI_SYNCICACHE 3 /* sync icache for pages */
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#define IPI_KPREEMPT 4 /* schedule a kernel preemption */
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#define IPI_SUSPEND 5 /* DDB suspend signaling */
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#define IPI_HALT 6 /* halt cpu */
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#define IPI_XCALL 7 /* xcall */
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#define IPI_GENERIC 8 /* generic IPI */
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#define IPI_WDOG 9 /* tickle a wdog */
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#define NIPIS 10
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#ifdef __INTR_PRIVATE
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struct splsw {
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int (*splsw_splhigh)(void);
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int (*splsw_splsched)(void);
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int (*splsw_splvm)(void);
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int (*splsw_splsoftserial)(void);
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int (*splsw_splsoftnet)(void);
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int (*splsw_splsoftbio)(void);
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int (*splsw_splsoftclock)(void);
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int (*splsw_splraise)(int);
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void (*splsw_spl0)(void);
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void (*splsw_splx)(int);
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int (*splsw_splhigh_noprof)(void);
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void (*splsw_splx_noprof)(int);
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void (*splsw__setsoftintr)(uint32_t);
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void (*splsw__clrsoftintr)(uint32_t);
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int (*splsw_splintr)(uint32_t *);
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void (*splsw_splcheck)(void);
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};
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struct ipl_sr_map {
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uint32_t sr_bits[_IPL_N];
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};
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#else
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struct splsw;
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#endif /* __INTR_PRIVATE */
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typedef int ipl_t;
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typedef struct {
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ipl_t _spl;
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} ipl_cookie_t;
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#ifdef _KERNEL
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#if 0
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#if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
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#define __HAVE_PREEMPTION 1
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#define SOFTINT_KPREEMPT (SOFTINT_COUNT+0)
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#endif
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#endif
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#ifdef __INTR_PRIVATE
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extern struct splsw mips_splsw;
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extern struct ipl_sr_map ipl_sr_map;
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#endif /* __INTR_PRIVATE */
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int splhigh(void);
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int __noprofile splhigh_noprof(void);
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int splsched(void);
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int splvm(void);
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int splsoftserial(void);
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int splsoftnet(void);
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int splsoftbio(void);
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int splsoftclock(void);
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int splraise(int);
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void splx(int);
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void __noprofile splx_noprof(int);
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void spl0(void);
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int splintr(uint32_t *);
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void _setsoftintr(uint32_t);
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void _clrsoftintr(uint32_t);
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struct cpu_info;
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void ipi_init(struct cpu_info *);
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void ipi_process(struct cpu_info *, uint64_t);
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/*
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* These make no sense *NOT* to be inlined.
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*/
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static inline ipl_cookie_t
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makeiplcookie(ipl_t s)
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{
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return (ipl_cookie_t){._spl = s};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return splraise(icookie._spl);
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}
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#endif /* _KERNEL */
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#endif /* _MIPS_INTR_H_ */
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