141 lines
4.6 KiB
C
141 lines
4.6 KiB
C
/* $NetBSD: cache_r5900.h,v 1.10 2020/07/26 08:08:41 simonb Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define CACHE_R5900_SIZE_I 16384
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#define CACHE_R5900_SIZE_D 8192
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#define CACHE_R5900_LSIZE_I 64
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#define CACHE_R5900_LSIZE_D 64
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#define CACHEOP_R5900_IINV_I 0x07 /* INDEX INVALIDATE */
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#define CACHEOP_R5900_HINV_I 0x0b /* HIT INVALIDATE */
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#define CACHEOP_R5900_IWBINV_D 0x14
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/* INDEX WRITE BACK INVALIDATE */
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#define CACHEOP_R5900_ILTG_D 0x10 /* INDEX LOAD TAG */
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#define CACHEOP_R5900_ISTG_D 0x12 /* INDEX STORE TAG */
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#define CACHEOP_R5900_IINV_D 0x16 /* INDEX INVALIDATE */
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#define CACHEOP_R5900_HINV_D 0x1a /* HIT INVALIDATE */
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#define CACHEOP_R5900_HWBINV_D 0x18 /* HIT WRITEBACK INVALIDATE */
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#define CACHEOP_R5900_ILDT_D 0x11 /* INDEX LOAD DATA */
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#define CACHEOP_R5900_ISDT_D 0x13 /* INDEX STORE DATA */
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#define CACHEOP_R5900_HWB_D 0x1c
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/* HIT WRITEBACK W/O INVALIDATE */
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#if !defined(_LOCORE)
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#define cache_op_r5900_line_64(va, op) \
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do { \
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__asm volatile( \
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".set noreorder \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 0(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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#define cache_r5900_op_4lines_64(va, op) \
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do { \
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__asm volatile( \
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".set noreorder \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 0(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 64(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 128(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 192(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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#define cache_r5900_op_4lines_64_2way(va, op) \
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do { \
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__asm volatile( \
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".set noreorder \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 0(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 1(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 64(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 65(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 128(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 129(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 192(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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"cache %1, 193(%0) \n\t" \
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"sync.l \n\t" \
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"sync.p \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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void r5900_icache_sync_all_64(void);
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void r5900_icache_sync_range_64(register_t, vsize_t);
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void r5900_icache_sync_range_index_64(vaddr_t, vsize_t);
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void r5900_pdcache_wbinv_all_64(void);
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void r5900_pdcache_wbinv_range_64(register_t, vsize_t);
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void r5900_pdcache_wbinv_range_index_64(vaddr_t, vsize_t);
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void r5900_pdcache_inv_range_64(register_t, vsize_t);
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void r5900_pdcache_wb_range_64(register_t, vsize_t);
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#endif /* !_LOCORE */
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