126 lines
5.0 KiB
C
126 lines
5.0 KiB
C
/* $NetBSD: cache_ls2.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
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/*-
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* Copyright (c) 2009 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_CACHE_LS2_H_
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#define _MIPS_CACHE_LS2_H_
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/*
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* Cache definitions/operations for Loongson-style caches.
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*/
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#define CACHEOP_LS2_I_INDEX_INV 0
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#define CACHEOP_LS2_D_INDEX_WB_INV 1
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#define CACHEOP_LS2_S_INDEX_WB_INV 3
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#define CACHEOP_LS2_D_HIT_INV 17
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#define CACHEOP_LS2_S_HIT_INV 19
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#define CACHEOP_LS2_D_HIT_WB_INV 21
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#define CACHEOP_LS2_S_HIT_WB_INV 23
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#if !defined(_LOCORE)
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/*
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* The way is encoded in the bottom 2 bits of VA.
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*/
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#define cache_op_ls2_8line_4way(va, op) \
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__asm volatile( \
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".set noreorder \n\t" \
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"cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
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"cache %1, 0x40(%0); cache %1, 0x60(%0) \n\t" \
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"cache %1, 0x80(%0); cache %1, 0xa0(%0) \n\t" \
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"cache %1, 0xc0(%0); cache %1, 0xe0(%0) \n\t" \
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"cache %1, 0x01(%0); cache %1, 0x21(%0) \n\t" \
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"cache %1, 0x41(%0); cache %1, 0x61(%0) \n\t" \
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"cache %1, 0x81(%0); cache %1, 0xa1(%0) \n\t" \
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"cache %1, 0xc1(%0); cache %1, 0xe1(%0) \n\t" \
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"cache %1, 0x02(%0); cache %1, 0x22(%0) \n\t" \
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"cache %1, 0x42(%0); cache %1, 0x62(%0) \n\t" \
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"cache %1, 0x82(%0); cache %1, 0xa2(%0) \n\t" \
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"cache %1, 0xc2(%0); cache %1, 0xe2(%0) \n\t" \
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"cache %1, 0x03(%0); cache %1, 0x23(%0) \n\t" \
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"cache %1, 0x43(%0); cache %1, 0x63(%0) \n\t" \
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"cache %1, 0x83(%0); cache %1, 0xa3(%0) \n\t" \
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"cache %1, 0xc3(%0); cache %1, 0xe3(%0) \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory");
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#define cache_op_ls2_line_4way(va, op) \
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__asm volatile( \
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".set noreorder \n\t" \
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"cache %1, 0(%0); cache %1, 1(%0) \n\t" \
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"cache %1, 2(%0); cache %1, 3(%0) \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory");
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#define cache_op_ls2_8line(va, op) \
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__asm volatile( \
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".set noreorder \n\t" \
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"cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
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"cache %1, 0x40(%0); cache %1, 0x60(%0) \n\t" \
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"cache %1, 0x80(%0); cache %1, 0xa0(%0) \n\t" \
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"cache %1, 0xc0(%0); cache %1, 0xe0(%0) \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory");
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#define cache_op_ls2_line(va, op) \
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__asm volatile( \
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".set noreorder \n\t" \
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"cache %1, 0(%0) \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory");
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void ls2_icache_sync_all(void);
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void ls2_icache_sync_range(register_t, vsize_t);
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void ls2_icache_sync_range_index(vaddr_t, vsize_t);
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void ls2_pdcache_wbinv_all(void);
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void ls2_pdcache_wbinv_range(register_t, vsize_t);
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void ls2_pdcache_wbinv_range_index(vaddr_t, vsize_t);
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void ls2_pdcache_inv_range(register_t, vsize_t);
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void ls2_pdcache_wb_range(register_t, vsize_t);
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void ls2_sdcache_wbinv_all(void);
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void ls2_sdcache_wbinv_range(register_t, vsize_t);
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void ls2_sdcache_wbinv_range_index(vaddr_t, vsize_t);
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void ls2_sdcache_inv_range(register_t, vsize_t);
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void ls2_sdcache_wb_range(register_t, vsize_t);
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#endif /* !_LOCORE */
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#endif /* !_MIPS_CACHE_LS2_H_ */
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