77 lines
3.0 KiB
C
77 lines
3.0 KiB
C
/* $NetBSD: imx_ahcisatareg.h,v 1.2 2024/02/07 04:20:27 msaitoh Exp $ */
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/*
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* Copyright (c) 2014 Ryo Shimizu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_NXP_IMX_AHCISATAREG_H_
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#define _ARM_NXP_IMX_AHCISATAREG_H_
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#define SATA_CAP 0x00000000
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#define SATA_CAP_SSS __BIT(27)
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#define SATA_PI 0x0000000c
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#define SATA_PI_PI __BIT(0)
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#define SATA_BISTAFR 0x000000a0
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#define SATA_BISTCR 0x000000a4
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#define SATA_BISTFCTR 0x000000a8
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#define SATA_BISTSR 0x000000ac
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#define SATA_OOBR 0x000000bc
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#define SATA_GPCR 0x000000d0
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#define SATA_GPSR 0x000000d4
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#define SATA_TIMER1MS 0x000000e0
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#define SATA_TESTR 0x000000f4
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#define SATA_VERSIONR 0x000000f8
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#define SATA_P0DMACR 0x00000170
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#define SATA_P0DMACR_RXTS(n) __SHIFTIN(n, __BITS(7, 4))
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#define SATA_P0DMACR_TXTS(n) __SHIFTIN(n, __BITS(3, 0))
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#define SATA_P0PHYCR 0x00000178
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#define SATA_P0PHYCR_CR_READ __BIT(19)
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#define SATA_P0PHYCR_CR_WRITE __BIT(18)
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#define SATA_P0PHYCR_CR_CAP_DATA __BIT(17)
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#define SATA_P0PHYCR_CR_CAP_ADDR __BIT(16)
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#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff)
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#define SATA_P0PHYSR 0x0000017c
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#define SATA_P0PHYSR_CR_ACK __BIT(18)
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#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff)
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/* phy registers */
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#define SATA_PHY_CLOCK_CTL_OVRD 0x0013
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#define SATA_PHY_CLOCK_CTL_OVRD_MPLL_PWRON __BIT(2)
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#define SATA_PHY_CLOCK_RESET 0x7f3f
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#define SATA_PHY_CLOCK_RESET_RST __BIT(0)
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#define SATA_PHY_LANE0_OUT_STAT 0x2003
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#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE __BIT(1)
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#define SATA_PHY_LANE0_TX_OVRD 0x2004
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#define SATA_PHY_LANE0_TX_OVRD_TX_EN(n) __SHIFTIN(n, __BITS(3, 1))
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#define SATA_PHY_LANE0_RX_OVRD 0x2005
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#define SATA_PHY_LANE0_RX_OVRD_RX_EN __BIT(2)
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#define SATA_PHY_LANE0_RX_OVRD_RX_PLL_PWRON __BIT(1)
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#endif /* _ARM_NXP_IMX_AHCISATAREG_H_ */
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