322 lines
8.5 KiB
C
322 lines
8.5 KiB
C
/* $NetBSD: imx8mq_ccm.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */
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/*-
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* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _IMX8MQ_CCM_H
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#define _IMX8MQ_CCM_H
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/*
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* Clocks
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*/
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#define CLK_DUMMY 0
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#define CLK_32K 1
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#define CLK_25M 2
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#define CLK_27M 3
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#define CLK_EXT1 4
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#define CLK_EXT2 5
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#define CLK_EXT3 6
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#define CLK_EXT4 7
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#define ARM_PLL_REF_SEL 8
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#define ARM_PLL_REF_DIV 9
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#define ARM_PLL 10
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#define ARM_PLL_BYPASS 11
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#define ARM_PLL_OUT 12
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#define GPU_PLL_REF_SEL 13
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#define GPU_PLL_REF_DIV 14
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#define GPU_PLL 15
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#define GPU_PLL_BYPASS 16
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#define GPU_PLL_OUT 17
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#define VPU_PLL_REF_SEL 18
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#define VPU_PLL_REF_DIV 19
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#define VPU_PLL 20
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#define VPU_PLL_BYPASS 21
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#define VPU_PLL_OUT 22
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#define AUDIO_PLL1_REF_SEL 23
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#define AUDIO_PLL1_REF_DIV 24
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#define AUDIO_PLL1 25
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#define AUDIO_PLL1_BYPASS 26
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#define AUDIO_PLL1_OUT 27
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#define AUDIO_PLL2_REF_SEL 28
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#define AUDIO_PLL2_REF_DIV 29
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#define AUDIO_PLL2 30
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#define AUDIO_PLL2_BYPASS 31
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#define AUDIO_PLL2_OUT 32
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#define VIDEO_PLL1_REF_SEL 33
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#define VIDEO_PLL1_REF_DIV 34
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#define VIDEO_PLL1 35
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#define VIDEO_PLL1_BYPASS 36
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#define VIDEO_PLL1_OUT 37
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#define SYS1_PLL1_REF_SEL 38
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#define SYS1_PLL1_REF_DIV 39
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#define SYS1_PLL1 40
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#define SYS1_PLL1_OUT 41
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#define SYS1_PLL1_OUT_DIV 42
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#define SYS1_PLL2 43
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#define SYS1_PLL2_DIV 44
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#define SYS1_PLL2_OUT 45
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#define SYS2_PLL1_REF_SEL 46
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#define SYS2_PLL1_REF_DIV 47
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#define SYS2_PLL1 48
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#define SYS2_PLL1_OUT 49
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#define SYS2_PLL1_OUT_DIV 50
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#define SYS2_PLL2 51
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#define SYS2_PLL2_DIV 52
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#define SYS2_PLL2_OUT 53
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#define SYS3_PLL1_REF_SEL 54
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#define SYS3_PLL1_REF_DIV 55
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#define SYS3_PLL1 56
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#define SYS3_PLL1_OUT 57
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#define SYS3_PLL1_OUT_DIV 58
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#define SYS3_PLL2 59
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#define SYS3_PLL2_DIV 60
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#define SYS3_PLL2_OUT 61
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#define DRAM_PLL1_REF_SEL 62
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#define DRAM_PLL1_REF_DIV 63
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#define DRAM_PLL1 64
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#define DRAM_PLL1_OUT 65
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#define DRAM_PLL1_OUT_DIV 66
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#define DRAM_PLL2 67
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#define DRAM_PLL2_DIV 68
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#define DRAM_PLL2_OUT 69
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#define SYS1_PLL_40M 70
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#define SYS1_PLL_80M 71
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#define SYS1_PLL_100M 72
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#define SYS1_PLL_133M 73
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#define SYS1_PLL_160M 74
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#define SYS1_PLL_200M 75
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#define SYS1_PLL_266M 76
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#define SYS1_PLL_400M 77
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#define SYS1_PLL_800M 78
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#define SYS2_PLL_50M 79
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#define SYS2_PLL_100M 80
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#define SYS2_PLL_125M 81
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#define SYS2_PLL_166M 82
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#define SYS2_PLL_200M 83
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#define SYS2_PLL_250M 84
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#define SYS2_PLL_333M 85
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#define SYS2_PLL_500M 86
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#define SYS2_PLL_1000M 87
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#define CLK_A53_SRC 88
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#define CLK_A53_CG 89
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#define CLK_A53_DIV 90
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#define CLK_M4_SRC 91
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#define CLK_M4_CG 92
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#define CLK_M4_DIV 93
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#define CLK_VPU_SRC 94
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#define CLK_VPU_CG 95
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#define CLK_VPU_DIV 96
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#define CLK_GPU_CORE_SRC 97
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#define CLK_GPU_CORE_CG 98
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#define CLK_GPU_CORE_DIV 99
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#define CLK_GPU_SHADER_SRC 100
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#define CLK_GPU_SHADER_CG 101
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#define CLK_GPU_SHADER_DIV 102
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#define CLK_MAIN_AXI 103
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#define CLK_ENET_AXI 104
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#define CLK_NAND_USDHC_BUS 105
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#define CLK_VPU_BUS 106
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#define CLK_DISP_AXI 107
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#define CLK_DISP_APB 108
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#define CLK_DISP_RTRM 109
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#define CLK_USB_BUS 110
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#define CLK_GPU_AXI 111
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#define CLK_GPU_AHB 112
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#define CLK_NOC 113
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#define CLK_NOC_APB 115
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#define CLK_AHB 116
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#define CLK_AUDIO_AHB 117
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#define CLK_DRAM_ALT 118
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#define CLK_DRAM_APB 119
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#define CLK_VPU_G1 120
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#define CLK_VPU_G2 121
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#define CLK_DISP_DTRC 122
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#define CLK_DISP_DC8000 123
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#define CLK_PCIE1_CTRL 124
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#define CLK_PCIE1_PHY 125
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#define CLK_PCIE1_AUX 126
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#define CLK_DC_PIXEL 127
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#define CLK_LCDIF_PIXEL 128
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#define CLK_SAI1 129
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#define CLK_SAI2 130
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#define CLK_SAI3 131
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#define CLK_SAI4 132
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#define CLK_SAI5 133
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#define CLK_SAI6 134
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#define CLK_SPDIF1 135
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#define CLK_SPDIF2 136
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#define CLK_ENET_REF 137
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#define CLK_ENET_TIMER 138
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#define CLK_ENET_PHY_REF 139
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#define CLK_NAND 140
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#define CLK_QSPI 141
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#define CLK_USDHC1 142
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#define CLK_USDHC2 143
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#define CLK_I2C1 144
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#define CLK_I2C2 145
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#define CLK_I2C3 146
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#define CLK_I2C4 147
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#define CLK_UART1 148
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#define CLK_UART2 149
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#define CLK_UART3 150
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#define CLK_UART4 151
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#define CLK_USB_CORE_REF 152
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#define CLK_USB_PHY_REF 153
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#define CLK_ECSPI1 154
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#define CLK_ECSPI2 155
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#define CLK_PWM1 156
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#define CLK_PWM2 157
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#define CLK_PWM3 158
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#define CLK_PWM4 159
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#define CLK_GPT1 160
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#define CLK_WDOG 161
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#define CLK_WRCLK 162
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#define CLK_DSI_CORE 163
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#define CLK_DSI_PHY_REF 164
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#define CLK_DSI_DBI 165
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#define CLK_DSI_ESC 166
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#define CLK_CSI1_CORE 167
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#define CLK_CSI1_PHY_REF 168
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#define CLK_CSI1_ESC 169
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#define CLK_CSI2_CORE 170
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#define CLK_CSI2_PHY_REF 171
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#define CLK_CSI2_ESC 172
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#define CLK_PCIE2_CTRL 173
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#define CLK_PCIE2_PHY 174
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#define CLK_PCIE2_AUX 175
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#define CLK_ECSPI3 176
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#define CLK_A53_ROOT 177
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#define CLK_DRAM_ROOT 178
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#define CLK_ECSPI1_ROOT 179
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#define CLK_ECSPI2_ROOT 180
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#define CLK_ECSPI3_ROOT 181
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#define CLK_ENET1_ROOT 182
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#define CLK_GPT1_ROOT 183
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#define CLK_I2C1_ROOT 184
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#define CLK_I2C2_ROOT 185
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#define CLK_I2C3_ROOT 186
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#define CLK_I2C4_ROOT 187
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#define CLK_M4_ROOT 188
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#define CLK_PCIE1_ROOT 189
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#define CLK_PCIE2_ROOT 190
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#define CLK_PWM1_ROOT 191
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#define CLK_PWM2_ROOT 192
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#define CLK_PWM3_ROOT 193
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#define CLK_PWM4_ROOT 194
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#define CLK_QSPI_ROOT 195
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#define CLK_SAI1_ROOT 196
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#define CLK_SAI2_ROOT 197
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#define CLK_SAI3_ROOT 198
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#define CLK_SAI4_ROOT 199
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#define CLK_SAI5_ROOT 200
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#define CLK_SAI6_ROOT 201
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#define CLK_UART1_ROOT 202
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#define CLK_UART2_ROOT 203
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#define CLK_UART3_ROOT 204
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#define CLK_UART4_ROOT 205
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#define CLK_USB1_CTRL_ROOT 206
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#define CLK_USB2_CTRL_ROOT 207
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#define CLK_USB1_PHY_ROOT 208
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#define CLK_USB2_PHY_ROOT 209
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#define CLK_USDHC1_ROOT 210
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#define CLK_USDHC2_ROOT 211
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#define CLK_WDOG1_ROOT 212
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#define CLK_WDOG2_ROOT 213
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#define CLK_WDOG3_ROOT 214
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#define CLK_GPU_ROOT 215
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#define CLK_HEVC_ROOT 216
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#define CLK_AVC_ROOT 217
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#define CLK_VP9_ROOT 218
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#define CLK_HEVC_INTER_ROOT 219
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#define CLK_DISP_ROOT 220
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#define CLK_HDMI_ROOT 221
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#define CLK_HDMI_PHY_ROOT 222
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#define CLK_VPU_DEC_ROOT 223
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#define CLK_CSI1_ROOT 224
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#define CLK_CSI2_ROOT 225
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#define CLK_RAWNAND_ROOT 226
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#define CLK_SDMA1_ROOT 227
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#define CLK_SDMA2_ROOT 228
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#define CLK_VPU_G1_ROOT 229
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#define CLK_VPU_G2_ROOT 230
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#define SYS1_PLL_OUT 231
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#define SYS2_PLL_OUT 232
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#define SYS3_PLL_OUT 233
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#define DRAM_PLL_OUT 234
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#define GPT_3M_CLK 235
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#define CLK_IPG_ROOT 236
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#define CLK_IPG_AUDIO_ROOT 237
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#define CLK_SAI1_IPG 238
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#define CLK_SAI2_IPG 239
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#define CLK_SAI3_IPG 240
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#define CLK_SAI4_IPG 241
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#define CLK_SAI5_IPG 242
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#define CLK_SAI6_IPG 243
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#define CLK_DSI_AHB 244
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#define CLK_DSI_IPG_DIV 245
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#define CLK_TMU_ROOT 246
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#define CLK_DISP_AXI_ROOT 247
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#define CLK_DISP_APB_ROOT 248
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#define CLK_DISP_RTRM_ROOT 249
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#define CLK_OCOTP_ROOT 250
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#define CLK_DRAM_ALT_ROOT 251
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#define CLK_DRAM_CORE 252
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#define CLK_MU_ROOT 253
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#define VIDEO2_PLL_OUT 254
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#define CLK_CLKO2 255
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#define CLK_NAND_USDHC_BUS_RAWNAND_CLK 256
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#define CLK_CLKO1 257
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#define CLK_ARM 258
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#define CLK_GPIO1_ROOT 259
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#define CLK_GPIO2_ROOT 260
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#define CLK_GPIO3_ROOT 261
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#define CLK_GPIO4_ROOT 262
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#define CLK_GPIO5_ROOT 263
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#define CLK_SNVS_ROOT 264
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#define CLK_GIC 265
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#define VIDEO2_PLL1_REF_SEL 266
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#define SYS1_PLL_40M_CG 267
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#define SYS1_PLL_80M_CG 268
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#define SYS1_PLL_100M_CG 269
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#define SYS1_PLL_133M_CG 270
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#define SYS1_PLL_160M_CG 271
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#define SYS1_PLL_200M_CG 272
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#define SYS1_PLL_266M_CG 273
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#define SYS1_PLL_400M_CG 274
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#define SYS1_PLL_800M_CG 275
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#define SYS2_PLL_50M_CG 276
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#define SYS2_PLL_100M_CG 277
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#define SYS2_PLL_125M_CG 278
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#define SYS2_PLL_166M_CG 279
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#define SYS2_PLL_200M_CG 280
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#define SYS2_PLL_250M_CG 281
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#define SYS2_PLL_333M_CG 282
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#define SYS2_PLL_500M_CG 283
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#define SYS2_PLL_1000M_CG 284
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#endif /* !_IMX8MQ_CCM_H */
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