483 lines
14 KiB
C
483 lines
14 KiB
C
/* $NetBSD: imx7d_ccm.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */
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/*-
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* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _IMX7D_CCM_H
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#define _IMX7D_CCM_H
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/*
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* Clocks
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*/
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#define OSC_24M_CLK 0
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#define PLL_ARM_MAIN 1
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#define PLL_ARM_MAIN_CLK 2
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#define PLL_ARM_MAIN_SRC 3
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#define PLL_ARM_MAIN_BYPASS 4
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#define PLL_SYS_MAIN 5
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#define PLL_SYS_MAIN_CLK 6
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#define PLL_SYS_MAIN_SRC 7
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#define PLL_SYS_MAIN_BYPASS 8
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#define PLL_SYS_MAIN_480M 9
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#define PLL_SYS_MAIN_240M 10
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#define PLL_SYS_MAIN_120M 11
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#define PLL_SYS_MAIN_480M_CLK 12
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#define PLL_SYS_MAIN_240M_CLK 13
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#define PLL_SYS_MAIN_120M_CLK 14
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#define PLL_SYS_PFD0_392M_CLK 15
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#define PLL_SYS_PFD0_196M 16
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#define PLL_SYS_PFD0_196M_CLK 17
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#define PLL_SYS_PFD1_332M_CLK 18
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#define PLL_SYS_PFD1_166M 19
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#define PLL_SYS_PFD1_166M_CLK 20
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#define PLL_SYS_PFD2_270M_CLK 21
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#define PLL_SYS_PFD2_135M 22
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#define PLL_SYS_PFD2_135M_CLK 23
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#define PLL_SYS_PFD3_CLK 24
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#define PLL_SYS_PFD4_CLK 25
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#define PLL_SYS_PFD5_CLK 26
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#define PLL_SYS_PFD6_CLK 27
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#define PLL_SYS_PFD7_CLK 28
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#define PLL_ENET_MAIN 29
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#define PLL_ENET_MAIN_CLK 30
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#define PLL_ENET_MAIN_SRC 31
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#define PLL_ENET_MAIN_BYPASS 32
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#define PLL_ENET_MAIN_500M 33
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#define PLL_ENET_MAIN_250M 34
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#define PLL_ENET_MAIN_125M 35
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#define PLL_ENET_MAIN_100M 36
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#define PLL_ENET_MAIN_50M 37
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#define PLL_ENET_MAIN_40M 38
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#define PLL_ENET_MAIN_25M 39
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#define PLL_ENET_MAIN_500M_CLK 40
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#define PLL_ENET_MAIN_250M_CLK 41
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#define PLL_ENET_MAIN_125M_CLK 42
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#define PLL_ENET_MAIN_100M_CLK 43
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#define PLL_ENET_MAIN_50M_CLK 44
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#define PLL_ENET_MAIN_40M_CLK 45
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#define PLL_ENET_MAIN_25M_CLK 46
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#define PLL_DRAM_MAIN 47
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#define PLL_DRAM_MAIN_CLK 48
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#define PLL_DRAM_MAIN_SRC 49
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#define PLL_DRAM_MAIN_BYPASS 50
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#define PLL_DRAM_MAIN_533M 51
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#define PLL_DRAM_MAIN_533M_CLK 52
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#define PLL_AUDIO_MAIN 53
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#define PLL_AUDIO_MAIN_CLK 54
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#define PLL_AUDIO_MAIN_SRC 55
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#define PLL_AUDIO_MAIN_BYPASS 56
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#define PLL_VIDEO_MAIN_CLK 57
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#define PLL_VIDEO_MAIN 58
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#define PLL_VIDEO_MAIN_SRC 59
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#define PLL_VIDEO_MAIN_BYPASS 60
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#define USB_MAIN_480M_CLK 61
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#define ARM_A7_ROOT_CLK 62
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#define ARM_A7_ROOT_SRC 63
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#define ARM_A7_ROOT_CG 64
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#define ARM_A7_ROOT_DIV 65
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#define ARM_M4_ROOT_CLK 66
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#define ARM_M4_ROOT_SRC 67
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#define ARM_M4_ROOT_CG 68
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#define ARM_M4_ROOT_DIV 69
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#define ARM_M0_ROOT_CLK 70
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#define ARM_M0_ROOT_SRC 71
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#define ARM_M0_ROOT_CG 72
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#define ARM_M0_ROOT_DIV 73
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#define MAIN_AXI_ROOT_CLK 74
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#define MAIN_AXI_ROOT_SRC 75
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#define MAIN_AXI_ROOT_CG 76
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#define MAIN_AXI_ROOT_DIV 77
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#define DISP_AXI_ROOT_CLK 78
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#define DISP_AXI_ROOT_SRC 79
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#define DISP_AXI_ROOT_CG 80
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#define DISP_AXI_ROOT_DIV 81
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#define ENET_AXI_ROOT_CLK 82
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#define ENET_AXI_ROOT_SRC 83
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#define ENET_AXI_ROOT_CG 84
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#define ENET_AXI_ROOT_DIV 85
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#define NAND_USDHC_BUS_ROOT_CLK 86
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#define NAND_USDHC_BUS_ROOT_SRC 87
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#define NAND_USDHC_BUS_ROOT_CG 88
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#define NAND_USDHC_BUS_ROOT_DIV 89
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#define AHB_CHANNEL_ROOT_CLK 90
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#define AHB_CHANNEL_ROOT_SRC 91
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#define AHB_CHANNEL_ROOT_CG 92
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#define AHB_CHANNEL_ROOT_DIV 93
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#define DRAM_PHYM_ROOT_CLK 94
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#define DRAM_PHYM_ROOT_SRC 95
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#define DRAM_PHYM_ROOT_CG 96
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#define DRAM_PHYM_ROOT_DIV 97
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#define DRAM_ROOT_CLK 98
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#define DRAM_ROOT_SRC 99
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#define DRAM_ROOT_CG 100
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#define DRAM_ROOT_DIV 101
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#define DRAM_PHYM_ALT_ROOT_CLK 102
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#define DRAM_PHYM_ALT_ROOT_SRC 103
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#define DRAM_PHYM_ALT_ROOT_CG 104
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#define DRAM_PHYM_ALT_ROOT_DIV 105
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#define DRAM_ALT_ROOT_CLK 106
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#define DRAM_ALT_ROOT_SRC 107
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#define DRAM_ALT_ROOT_CG 108
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#define DRAM_ALT_ROOT_DIV 109
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#define USB_HSIC_ROOT_CLK 110
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#define USB_HSIC_ROOT_SRC 111
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#define USB_HSIC_ROOT_CG 112
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#define USB_HSIC_ROOT_DIV 113
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#define PCIE_CTRL_ROOT_CLK 114
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#define PCIE_CTRL_ROOT_SRC 115
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#define PCIE_CTRL_ROOT_CG 116
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#define PCIE_CTRL_ROOT_DIV 117
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#define PCIE_PHY_ROOT_CLK 118
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#define PCIE_PHY_ROOT_SRC 119
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#define PCIE_PHY_ROOT_CG 120
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#define PCIE_PHY_ROOT_DIV 121
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#define EPDC_PIXEL_ROOT_CLK 122
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#define EPDC_PIXEL_ROOT_SRC 123
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#define EPDC_PIXEL_ROOT_CG 124
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#define EPDC_PIXEL_ROOT_DIV 125
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#define LCDIF_PIXEL_ROOT_CLK 126
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#define LCDIF_PIXEL_ROOT_SRC 127
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#define LCDIF_PIXEL_ROOT_CG 128
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#define LCDIF_PIXEL_ROOT_DIV 129
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#define MIPI_DSI_ROOT_CLK 130
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#define MIPI_DSI_ROOT_SRC 131
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#define MIPI_DSI_ROOT_CG 132
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#define MIPI_DSI_ROOT_DIV 133
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#define MIPI_CSI_ROOT_CLK 134
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#define MIPI_CSI_ROOT_SRC 135
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#define MIPI_CSI_ROOT_CG 136
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#define MIPI_CSI_ROOT_DIV 137
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#define MIPI_DPHY_ROOT_CLK 138
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#define MIPI_DPHY_ROOT_SRC 139
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#define MIPI_DPHY_ROOT_CG 140
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#define MIPI_DPHY_ROOT_DIV 141
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#define SAI1_ROOT_CLK 142
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#define SAI1_ROOT_SRC 143
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#define SAI1_ROOT_CG 144
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#define SAI1_ROOT_DIV 145
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#define SAI2_ROOT_CLK 146
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#define SAI2_ROOT_SRC 147
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#define SAI2_ROOT_CG 148
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#define SAI2_ROOT_DIV 149
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#define SAI3_ROOT_CLK 150
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#define SAI3_ROOT_SRC 151
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#define SAI3_ROOT_CG 152
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#define SAI3_ROOT_DIV 153
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#define SPDIF_ROOT_CLK 154
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#define SPDIF_ROOT_SRC 155
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#define SPDIF_ROOT_CG 156
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#define SPDIF_ROOT_DIV 157
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#define ENET1_IPG_ROOT_CLK 158
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#define ENET1_REF_ROOT_SRC 159
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#define ENET1_REF_ROOT_CG 160
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#define ENET1_REF_ROOT_DIV 161
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#define ENET1_TIME_ROOT_CLK 162
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#define ENET1_TIME_ROOT_SRC 163
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#define ENET1_TIME_ROOT_CG 164
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#define ENET1_TIME_ROOT_DIV 165
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#define ENET2_IPG_ROOT_CLK 166
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#define ENET2_REF_ROOT_SRC 167
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#define ENET2_REF_ROOT_CG 168
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#define ENET2_REF_ROOT_DIV 169
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#define ENET2_TIME_ROOT_CLK 170
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#define ENET2_TIME_ROOT_SRC 171
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#define ENET2_TIME_ROOT_CG 172
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#define ENET2_TIME_ROOT_DIV 173
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#define ENET_PHY_REF_ROOT_CLK 174
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#define ENET_PHY_REF_ROOT_SRC 175
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#define ENET_PHY_REF_ROOT_CG 176
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#define ENET_PHY_REF_ROOT_DIV 177
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#define EIM_ROOT_CLK 178
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#define EIM_ROOT_SRC 179
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#define EIM_ROOT_CG 180
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#define EIM_ROOT_DIV 181
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#define NAND_ROOT_CLK 182
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#define NAND_ROOT_SRC 183
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#define NAND_ROOT_CG 184
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#define NAND_ROOT_DIV 185
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#define QSPI_ROOT_CLK 186
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#define QSPI_ROOT_SRC 187
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#define QSPI_ROOT_CG 188
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#define QSPI_ROOT_DIV 189
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#define USDHC1_ROOT_CLK 190
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#define USDHC1_ROOT_SRC 191
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#define USDHC1_ROOT_CG 192
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#define USDHC1_ROOT_DIV 193
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#define USDHC2_ROOT_CLK 194
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#define USDHC2_ROOT_SRC 195
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#define USDHC2_ROOT_CG 196
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#define USDHC2_ROOT_DIV 197
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#define USDHC3_ROOT_CLK 198
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#define USDHC3_ROOT_SRC 199
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#define USDHC3_ROOT_CG 200
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#define USDHC3_ROOT_DIV 201
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#define CAN1_ROOT_CLK 202
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#define CAN1_ROOT_SRC 203
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#define CAN1_ROOT_CG 204
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#define CAN1_ROOT_DIV 205
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#define CAN2_ROOT_CLK 206
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#define CAN2_ROOT_SRC 207
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#define CAN2_ROOT_CG 208
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#define CAN2_ROOT_DIV 209
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#define I2C1_ROOT_CLK 210
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#define I2C1_ROOT_SRC 211
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#define I2C1_ROOT_CG 212
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#define I2C1_ROOT_DIV 213
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#define I2C2_ROOT_CLK 214
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#define I2C2_ROOT_SRC 215
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#define I2C2_ROOT_CG 216
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#define I2C2_ROOT_DIV 217
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#define I2C3_ROOT_CLK 218
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#define I2C3_ROOT_SRC 219
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#define I2C3_ROOT_CG 220
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#define I2C3_ROOT_DIV 221
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#define I2C4_ROOT_CLK 222
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#define I2C4_ROOT_SRC 223
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#define I2C4_ROOT_CG 224
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#define I2C4_ROOT_DIV 225
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#define UART1_ROOT_CLK 226
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#define UART1_ROOT_SRC 227
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#define UART1_ROOT_CG 228
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#define UART1_ROOT_DIV 229
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#define UART2_ROOT_CLK 230
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#define UART2_ROOT_SRC 231
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#define UART2_ROOT_CG 232
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#define UART2_ROOT_DIV 233
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#define UART3_ROOT_CLK 234
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#define UART3_ROOT_SRC 235
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#define UART3_ROOT_CG 236
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#define UART3_ROOT_DIV 237
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#define UART4_ROOT_CLK 238
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#define UART4_ROOT_SRC 239
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#define UART4_ROOT_CG 240
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#define UART4_ROOT_DIV 241
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#define UART5_ROOT_CLK 242
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#define UART5_ROOT_SRC 243
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#define UART5_ROOT_CG 244
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#define UART5_ROOT_DIV 245
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#define UART6_ROOT_CLK 246
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#define UART6_ROOT_SRC 247
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#define UART6_ROOT_CG 248
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#define UART6_ROOT_DIV 249
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#define UART7_ROOT_CLK 250
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#define UART7_ROOT_SRC 251
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#define UART7_ROOT_CG 252
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#define UART7_ROOT_DIV 253
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#define ECSPI1_ROOT_CLK 254
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#define ECSPI1_ROOT_SRC 255
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#define ECSPI1_ROOT_CG 256
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#define ECSPI1_ROOT_DIV 257
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#define ECSPI2_ROOT_CLK 258
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#define ECSPI2_ROOT_SRC 259
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#define ECSPI2_ROOT_CG 260
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#define ECSPI2_ROOT_DIV 261
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#define ECSPI3_ROOT_CLK 262
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#define ECSPI3_ROOT_SRC 263
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#define ECSPI3_ROOT_CG 264
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#define ECSPI3_ROOT_DIV 265
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#define ECSPI4_ROOT_CLK 266
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#define ECSPI4_ROOT_SRC 267
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#define ECSPI4_ROOT_CG 268
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#define ECSPI4_ROOT_DIV 269
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#define PWM1_ROOT_CLK 270
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#define PWM1_ROOT_SRC 271
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#define PWM1_ROOT_CG 272
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#define PWM1_ROOT_DIV 273
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#define PWM2_ROOT_CLK 274
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#define PWM2_ROOT_SRC 275
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#define PWM2_ROOT_CG 276
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#define PWM2_ROOT_DIV 277
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#define PWM3_ROOT_CLK 278
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#define PWM3_ROOT_SRC 279
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#define PWM3_ROOT_CG 280
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#define PWM3_ROOT_DIV 281
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#define PWM4_ROOT_CLK 282
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#define PWM4_ROOT_SRC 283
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#define PWM4_ROOT_CG 284
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#define PWM4_ROOT_DIV 285
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#define FLEXTIMER1_ROOT_CLK 286
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#define FLEXTIMER1_ROOT_SRC 287
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#define FLEXTIMER1_ROOT_CG 288
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#define FLEXTIMER1_ROOT_DIV 289
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#define FLEXTIMER2_ROOT_CLK 290
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#define FLEXTIMER2_ROOT_SRC 291
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#define FLEXTIMER2_ROOT_CG 292
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#define FLEXTIMER2_ROOT_DIV 293
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#define SIM1_ROOT_CLK 294
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#define SIM1_ROOT_SRC 295
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#define SIM1_ROOT_CG 296
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#define SIM1_ROOT_DIV 297
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#define SIM2_ROOT_CLK 298
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#define SIM2_ROOT_SRC 299
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#define SIM2_ROOT_CG 300
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#define SIM2_ROOT_DIV 301
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#define GPT1_ROOT_CLK 302
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#define GPT1_ROOT_SRC 303
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#define GPT1_ROOT_CG 304
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#define GPT1_ROOT_DIV 305
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#define GPT2_ROOT_CLK 306
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#define GPT2_ROOT_SRC 307
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#define GPT2_ROOT_CG 308
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#define GPT2_ROOT_DIV 309
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#define GPT3_ROOT_CLK 310
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#define GPT3_ROOT_SRC 311
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#define GPT3_ROOT_CG 312
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#define GPT3_ROOT_DIV 313
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#define GPT4_ROOT_CLK 314
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#define GPT4_ROOT_SRC 315
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#define GPT4_ROOT_CG 316
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#define GPT4_ROOT_DIV 317
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#define TRACE_ROOT_CLK 318
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#define TRACE_ROOT_SRC 319
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#define TRACE_ROOT_CG 320
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#define TRACE_ROOT_DIV 321
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#define WDOG1_ROOT_CLK 322
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#define WDOG_ROOT_SRC 323
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#define WDOG_ROOT_CG 324
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#define WDOG_ROOT_DIV 325
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#define CSI_MCLK_ROOT_CLK 326
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#define CSI_MCLK_ROOT_SRC 327
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#define CSI_MCLK_ROOT_CG 328
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#define CSI_MCLK_ROOT_DIV 329
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#define AUDIO_MCLK_ROOT_CLK 330
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#define AUDIO_MCLK_ROOT_SRC 331
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#define AUDIO_MCLK_ROOT_CG 332
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#define AUDIO_MCLK_ROOT_DIV 333
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#define WRCLK_ROOT_CLK 334
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#define WRCLK_ROOT_SRC 335
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#define WRCLK_ROOT_CG 336
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#define WRCLK_ROOT_DIV 337
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#define CLKO1_ROOT_SRC 338
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#define CLKO1_ROOT_CG 339
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#define CLKO1_ROOT_DIV 340
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#define CLKO2_ROOT_SRC 341
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#define CLKO2_ROOT_CG 342
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#define CLKO2_ROOT_DIV 343
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#define MAIN_AXI_ROOT_PRE_DIV 344
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#define DISP_AXI_ROOT_PRE_DIV 345
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#define ENET_AXI_ROOT_PRE_DIV 346
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#define NAND_USDHC_BUS_ROOT_PRE_DIV 347
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#define AHB_CHANNEL_ROOT_PRE_DIV 348
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#define USB_HSIC_ROOT_PRE_DIV 349
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#define PCIE_CTRL_ROOT_PRE_DIV 350
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#define PCIE_PHY_ROOT_PRE_DIV 351
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#define EPDC_PIXEL_ROOT_PRE_DIV 352
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#define LCDIF_PIXEL_ROOT_PRE_DIV 353
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#define MIPI_DSI_ROOT_PRE_DIV 354
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#define MIPI_CSI_ROOT_PRE_DIV 355
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#define MIPI_DPHY_ROOT_PRE_DIV 356
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#define SAI1_ROOT_PRE_DIV 357
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#define SAI2_ROOT_PRE_DIV 358
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#define SAI3_ROOT_PRE_DIV 359
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#define SPDIF_ROOT_PRE_DIV 360
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#define ENET1_REF_ROOT_PRE_DIV 361
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#define ENET1_TIME_ROOT_PRE_DIV 362
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#define ENET2_REF_ROOT_PRE_DIV 363
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#define ENET2_TIME_ROOT_PRE_DIV 364
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#define ENET_PHY_REF_ROOT_PRE_DIV 365
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#define EIM_ROOT_PRE_DIV 366
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#define NAND_ROOT_PRE_DIV 367
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#define QSPI_ROOT_PRE_DIV 368
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#define USDHC1_ROOT_PRE_DIV 369
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#define USDHC2_ROOT_PRE_DIV 370
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#define USDHC3_ROOT_PRE_DIV 371
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#define CAN1_ROOT_PRE_DIV 372
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#define CAN2_ROOT_PRE_DIV 373
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#define I2C1_ROOT_PRE_DIV 374
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#define I2C2_ROOT_PRE_DIV 375
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#define I2C3_ROOT_PRE_DIV 376
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#define I2C4_ROOT_PRE_DIV 377
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#define UART1_ROOT_PRE_DIV 378
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#define UART2_ROOT_PRE_DIV 379
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#define UART3_ROOT_PRE_DIV 380
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#define UART4_ROOT_PRE_DIV 381
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#define UART5_ROOT_PRE_DIV 382
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#define UART6_ROOT_PRE_DIV 383
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#define UART7_ROOT_PRE_DIV 384
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#define ECSPI1_ROOT_PRE_DIV 385
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#define ECSPI2_ROOT_PRE_DIV 386
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#define ECSPI3_ROOT_PRE_DIV 387
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#define ECSPI4_ROOT_PRE_DIV 388
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#define PWM1_ROOT_PRE_DIV 389
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#define PWM2_ROOT_PRE_DIV 390
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#define PWM3_ROOT_PRE_DIV 391
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#define PWM4_ROOT_PRE_DIV 392
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#define FLEXTIMER1_ROOT_PRE_DIV 393
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#define FLEXTIMER2_ROOT_PRE_DIV 394
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#define SIM1_ROOT_PRE_DIV 395
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#define SIM2_ROOT_PRE_DIV 396
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#define GPT1_ROOT_PRE_DIV 397
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#define GPT2_ROOT_PRE_DIV 398
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#define GPT3_ROOT_PRE_DIV 399
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#define GPT4_ROOT_PRE_DIV 400
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#define TRACE_ROOT_PRE_DIV 401
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#define WDOG_ROOT_PRE_DIV 402
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#define CSI_MCLK_ROOT_PRE_DIV 403
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#define AUDIO_MCLK_ROOT_PRE_DIV 404
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#define WRCLK_ROOT_PRE_DIV 405
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#define CLKO1_ROOT_PRE_DIV 406
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#define CLKO2_ROOT_PRE_DIV 407
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#define DRAM_PHYM_ALT_ROOT_PRE_DIV 408
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#define DRAM_ALT_ROOT_PRE_DIV 409
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#define LVDS1_IN_CLK 410
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#define LVDS1_OUT_SEL 411
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#define LVDS1_OUT_CLK 412
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#define CLK_DUMMY 413
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#define GPT_3M_CLK 414
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#define OCRAM_CLK 415
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#define OCRAM_S_CLK 416
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#define WDOG2_ROOT_CLK 417
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#define WDOG3_ROOT_CLK 418
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#define WDOG4_ROOT_CLK 419
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#define SDMA_CORE_CLK 420
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#define USB1_MAIN_480M_CLK 421
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#define USB_CTRL_CLK 422
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#define USB_PHY1_CLK 423
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#define USB_PHY2_CLK 424
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#define IPG_ROOT_CLK 425
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#define SAI1_IPG_CLK 426
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#define SAI2_IPG_CLK 427
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#define SAI3_IPG_CLK 428
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#define PLL_AUDIO_TEST_DIV 429
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#define PLL_AUDIO_POST_DIV 430
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#define PLL_VIDEO_TEST_DIV 431
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#define PLL_VIDEO_POST_DIV 432
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#define MU_ROOT_CLK 433
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#define SEMA4_HS_ROOT_CLK 434
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#define PLL_DRAM_TEST_DIV 435
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#define ADC_ROOT_CLK 436
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#define CLK_ARM 437
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#define CKIL 438
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#define OCOTP_CLK 439
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#define NAND_RAWNAND_CLK 440
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#define NAND_USDHC_BUS_RAWNAND_CLK 441
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#define SNVS_CLK 442
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#define CAAM_CLK 443
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#define KPP_ROOT_CLK 444
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#endif /* !_IMX7D_CCM_H */
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