316 lines
7.7 KiB
C
316 lines
7.7 KiB
C
/* $NetBSD: imx6_ccmvar.h,v 1.3 2023/05/04 13:25:07 bouyer Exp $ */
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/*
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* Copyright (c) 2012,2019 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_NXP_IMX6_CCMVAR_H_
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#define _ARM_NXP_IMX6_CCMVAR_H_
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#include <dev/clk/clk.h>
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#include <dev/clk/clk_backend.h>
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struct imx6ccm_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_space_handle_t sc_ioh_analog;
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struct clk_domain sc_clkdom;
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struct imx6_clk *sc_imx6_clks;
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int sc_imx6_clksize;
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};
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struct imxccm_init_parent;
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void imx6ccm_attach_common(device_t, struct imx6_clk *, int,
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struct imxccm_init_parent *);
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struct clk *imx6_get_clock(struct imx6ccm_softc *, const char *);
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struct imx6_clk *imx6_clk_find(struct imx6ccm_softc *sc, const char *);
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struct imxccm_init_parent {
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const char *clock;
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const char *parent;
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};
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enum imx6_clk_type {
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IMX6_CLK_FIXED,
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IMX6_CLK_FIXED_FACTOR,
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IMX6_CLK_PLL,
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IMX6_CLK_MUX,
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IMX6_CLK_GATE,
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IMX6_CLK_PFD,
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IMX6_CLK_DIV,
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};
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enum imx6_clk_reg {
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IMX6_CLK_REG_CCM,
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IMX6_CLK_REG_CCM_ANALOG,
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};
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enum imx6_clk_pll_type {
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IMX6_CLK_PLL_GENERIC,
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IMX6_CLK_PLL_SYS,
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IMX6_CLK_PLL_USB,
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IMX6_CLK_PLL_AUDIO_VIDEO,
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IMX6_CLK_PLL_ENET,
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};
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enum imx6_clk_div_type {
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IMX6_CLK_DIV_NORMAL,
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IMX6_CLK_DIV_BUSY,
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IMX6_CLK_DIV_TABLE,
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};
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enum imx6_clk_mux_type {
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IMX6_CLK_MUX_NORMAL,
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IMX6_CLK_MUX_BUSY,
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};
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struct imx6_clk_fixed {
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u_int rate;
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};
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struct imx6_clk_fixed_factor {
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u_int div;
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u_int mult;
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};
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struct imx6_clk_pfd {
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uint32_t reg;
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int index;
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};
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struct imx6_clk_pll {
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enum imx6_clk_pll_type type;
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uint32_t reg;
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uint32_t mask;
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uint32_t powerdown;
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unsigned long ref;
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};
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struct imx6_clk_div {
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enum imx6_clk_div_type type;
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enum imx6_clk_reg base;
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uint32_t reg;
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uint32_t mask;
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uint32_t busy_reg;
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uint32_t busy_mask;
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const int *tbl;
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};
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struct imx6_clk_mux {
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enum imx6_clk_mux_type type;
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enum imx6_clk_reg base;
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uint32_t reg;
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uint32_t mask;
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const char **parents;
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u_int nparents;
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uint32_t busy_reg;
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uint32_t busy_mask;
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};
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struct imx6_clk_gate {
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enum imx6_clk_reg base;
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uint32_t reg;
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uint32_t mask;
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uint32_t exclusive_mask;
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};
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struct imx6_clk {
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struct clk base; /* must be first */
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const char *parent;
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u_int refcnt;
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enum imx6_clk_type type;
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union {
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struct imx6_clk_fixed fixed;
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struct imx6_clk_fixed_factor fixed_factor;
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struct imx6_clk_pfd pfd;
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struct imx6_clk_pll pll;
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struct imx6_clk_div div;
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struct imx6_clk_mux mux;
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struct imx6_clk_gate gate;
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} clk;
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};
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#define CLK_FIXED(_name, _rate) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_FIXED, \
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.clk = { \
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.fixed = { \
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.rate = (_rate), \
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} \
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} \
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}
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#define CLK_FIXED_FACTOR(_name, _parent, _div, _mult) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_FIXED_FACTOR, \
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.parent = (_parent), \
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.clk = { \
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.fixed_factor = { \
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.div = (_div), \
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.mult = (_mult), \
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} \
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} \
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}
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#define CLK_PFD(_name, _parent, _reg, _index) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_PFD, \
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.parent = (_parent), \
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.clk = { \
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.pfd = { \
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.reg = (CCM_ANALOG_##_reg), \
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.index = (_index), \
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} \
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} \
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}
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#define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_PLL, \
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.parent = (_parent), \
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.clk = { \
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.pll = { \
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.type = (IMX6_CLK_PLL_##_type), \
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.reg = (CCM_ANALOG_##_reg), \
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.mask = (CCM_ANALOG_##_reg##_##_mask), \
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.powerdown = (CCM_ANALOG_##_reg##_##_powerdown), \
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.ref = (_ref), \
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} \
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} \
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}
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#define CLK_DIV(_name, _parent, _reg, _mask) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_DIV, \
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.parent = (_parent), \
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.clk = { \
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.div = { \
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.type = (IMX6_CLK_DIV_NORMAL), \
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.base = (IMX6_CLK_REG_CCM), \
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.reg = (CCM_##_reg), \
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.mask = (CCM_##_reg##_##_mask), \
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} \
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} \
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}
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#define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_DIV, \
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.parent = (_parent), \
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.clk = { \
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.div = { \
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.type = (IMX6_CLK_DIV_BUSY), \
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.base = (IMX6_CLK_REG_CCM), \
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.reg = (CCM_##_reg), \
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.mask = (CCM_##_reg##_##_mask), \
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.busy_reg = (CCM_##_busy_reg), \
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.busy_mask = (CCM_##_busy_reg##_##_busy_mask) \
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} \
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} \
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}
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#define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \
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.base = { .name = (_name) }, \
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.type = IMX6_CLK_DIV, \
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.parent = (_parent), \
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.clk = { \
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.div = { \
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.type = (IMX6_CLK_DIV_TABLE), \
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.base = (IMX6_CLK_REG_CCM_ANALOG), \
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.reg = (CCM_ANALOG_##_reg), \
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.mask = (CCM_ANALOG_##_reg##_##_mask), \
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.tbl = (_tbl) \
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} \
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} \
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}
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#define CLK_MUX(_name, _parents, _base, _reg, _mask) { \
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.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
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.type = IMX6_CLK_MUX, \
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.clk = { \
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.mux = { \
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.type = (IMX6_CLK_MUX_NORMAL), \
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.base = (IMX6_CLK_REG_##_base), \
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.reg = (_base##_##_reg), \
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.mask = (_base##_##_reg##_##_mask), \
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.parents = (_parents), \
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.nparents = __arraycount(_parents) \
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} \
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} \
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}
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#define CLK_MUX_BUSY(_name, _parents, _reg, _mask, _busy_reg, _busy_mask) { \
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.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
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.type = IMX6_CLK_MUX, \
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.clk = { \
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.mux = { \
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.type = (IMX6_CLK_MUX_BUSY), \
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.base = (IMX6_CLK_REG_CCM), \
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.reg = (CCM_##_reg), \
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.mask = (CCM_##_reg##_##_mask), \
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.parents = (_parents), \
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.nparents = __arraycount(_parents), \
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.busy_reg = (CCM_##_busy_reg), \
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.busy_mask = (CCM_##_busy_reg##_##_busy_mask) \
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} \
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} \
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}
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#define CLK_GATE(_name, _parent, _base, _reg, _mask) { \
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.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
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.type = IMX6_CLK_GATE, \
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.parent = (_parent), \
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.clk = { \
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.gate = { \
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.base = (IMX6_CLK_REG_##_base), \
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.reg = (_base##_##_reg), \
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.mask = (_base##_##_reg##_##_mask), \
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.exclusive_mask = 0 \
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} \
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} \
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}
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#define CLK_GATE_EXCLUSIVE(_name, _parent, _base, _reg, _mask, _exclusive_mask) { \
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.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
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.type = IMX6_CLK_GATE, \
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.parent = (_parent), \
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.clk = { \
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.gate = { \
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.base = (IMX6_CLK_REG_##_base), \
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.reg = (_base##_##_reg), \
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.mask = (_base##_##_reg##_##_mask), \
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.exclusive_mask = (_base##_##_reg##_##_exclusive_mask) \
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} \
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} \
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}
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#endif /* _ARM_NXP_IMX6_CCMVAR_H_ */
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