517 lines
16 KiB
C
517 lines
16 KiB
C
/* $NetBSD: mvsata_pci.c,v 1.10 2018/08/31 18:43:29 jdolecek Exp $ */
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/*
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* Copyright (c) 2008 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mvsata_pci.c,v 1.10 2018/08/31 18:43:29 jdolecek Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/pmf.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/ic/mvsatareg.h>
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#include <dev/ic/mvsatavar.h>
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#define MVSATA_PCI_HCARBITER_SPACE_OFFSET 0x20000
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#define MVSATA_PCI_COMMAND 0x00c00
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#define MVSATA_PCI_COMMAND_MWRITECOMBINE (1 << 4)
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#define MVSATA_PCI_COMMAND_MREADCOMBINE (1 << 5)
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#define MVSATA_PCI_SERRMASK 0x00c28
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#define MVSATA_PCI_MSITRIGGER 0x00c38
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#define MVSATA_PCI_MODE 0x00d00
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#define MVSATA_PCI_DISCTIMER 0x00d04
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#define MVSATA_PCI_EROMBAR 0x00d2c
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#define MVSATA_PCI_MAINCS 0x00d30
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#define MVSATA_PCI_MAINCS_SPM (1 << 2) /* stop pci master */
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#define MVSATA_PCI_MAINCS_PME (1 << 3) /* pci master empty */
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#define MVSATA_PCI_MAINCS_GSR (1 << 4) /* glab soft reset */
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#define MVSATA_PCI_E_IRQCAUSE 0x01900
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#define MVSATA_PCI_E_IRQMASK 0x01910
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#define MVSATA_PCI_XBARTIMEOUT 0x01d04
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#define MVSATA_PCI_ERRLOWADDR 0x01d40
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#define MVSATA_PCI_ERRHIGHADDR 0x01d44
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#define MVSATA_PCI_ERRATTRIBUTE 0x01d48
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#define MVSATA_PCI_ERRCOMMAND 0x01d50
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#define MVSATA_PCI_IRQCAUSE 0x01d58
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#define MVSATA_PCI_IRQMASK 0x01d5c
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#define MVSATA_PCI_MAINIRQCAUSE 0x01d60
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#define MVSATA_PCI_MAINIRQMASK 0x01d64
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#define MVSATA_PCI_MAINIRQ_SATAERR(hc, port) \
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(1 << (((port) << 1) + (hc) * 9))
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#define MVSATA_PCI_MAINIRQ_SATADONE(hc, port) \
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(1 << (((port) << 1) + (hc) * 9 + 1))
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#define MVSATA_PCI_MAINIRQ_SATACOALDONE(hc) (1 << ((hc) * 9 + 8))
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#define MVSATA_PCI_MAINIRQ_PCI (1 << 18)
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#define MVSATA_PCI_FLASHCTL 0x1046c
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#define MVSATA_PCI_GPIOPORTCTL 0x104f0
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#define MVSATA_PCI_RESETCFG 0x180d8
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#define MVSATA_PCI_DEV(psc) (psc->psc_sc.sc_wdcdev.sc_atac.atac_dev)
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struct mvsata_pci_softc {
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struct mvsata_softc psc_sc;
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pci_chipset_tag_t psc_pc;
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pcitag_t psc_tag;
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bus_space_tag_t psc_iot;
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bus_space_handle_t psc_ioh;
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void *psc_ih;
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};
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static int mvsata_pci_match(device_t, struct cfdata *, void *);
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static void mvsata_pci_attach(device_t, device_t, void *);
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static int mvsata_pci_detach(device_t, int);
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static int mvsata_pci_intr(void *);
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static bool mvsata_pci_resume(device_t, const pmf_qual_t *qual);
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static int mvsata_pci_sreset(struct mvsata_softc *);
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static int mvsata_pci_misc_reset(struct mvsata_softc *);
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static void mvsata_pci_enable_intr(struct mvsata_port *, int);
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CFATTACH_DECL_NEW(mvsata_pci, sizeof(struct mvsata_pci_softc),
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mvsata_pci_match, mvsata_pci_attach, mvsata_pci_detach, NULL);
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static const struct mvsata_product mvsata_pci_products[] = {
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#define PCI_VP(v, p) PCI_VENDOR_ ## v, PCI_PRODUCT_ ## v ## _ ## p
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{ PCI_VP(MARVELL, 88SX5040), 1, 4, gen1, 0 },
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{ PCI_VP(MARVELL, 88SX5041), 1, 4, gen1, 0 },
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{ PCI_VP(MARVELL, 88SX5080), 2, 4, gen1, 0 },
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{ PCI_VP(MARVELL, 88SX5081), 2, 4, gen1, 0 },
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{ PCI_VP(MARVELL, 88SX6040), 1, 4, gen2, 0 },
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{ PCI_VP(MARVELL, 88SX6041), 1, 4, gen2, 0 },
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{ PCI_VP(ADP2, 1420SA), 1, 4, gen2, 0 }, /* 88SX6041 */
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{ PCI_VP(MARVELL, 88SX6042), 1, 4, gen2e, 0 },
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{ PCI_VP(MARVELL, 88SX6080), 2, 4, gen2, MVSATA_FLAGS_PCIE },
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{ PCI_VP(MARVELL, 88SX6081), 2, 4, gen2, MVSATA_FLAGS_PCIE },
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{ PCI_VP(MARVELL, 88SX7042), 1, 4, gen2e, 0 },
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{ PCI_VP(ADP2, 1430SA), 1, 4, gen2e, 0 }, /* 88SX7042 */
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{ PCI_VP(TRIONES, ROCKETRAID_2310), 1, 4, gen2e, 0 },
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#undef PCI_VP
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};
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/*
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* mvsata_pci_match()
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* This function returns 2, because mvsata is high priority more than pciide.
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*/
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static int
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mvsata_pci_match(device_t parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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int i;
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for (i = 0; i < __arraycount(mvsata_pci_products); i++)
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if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor &&
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PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model)
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return 2;
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return 0;
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}
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static void
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mvsata_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct mvsata_pci_softc *psc = device_private(self);
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struct mvsata_softc *sc = &psc->psc_sc;
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pci_intr_handle_t intrhandle;
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pcireg_t csr;
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bus_size_t size;
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uint32_t reg, mask;
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int read_pre_amps, hc, port, rv, i;
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const char *intrstr;
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char intrbuf[PCI_INTRSTR_LEN];
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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sc->sc_model = PCI_PRODUCT(pa->pa_id);
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sc->sc_rev = PCI_REVISION(pa->pa_class);
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sc->sc_dmat = pa->pa_dmat;
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sc->sc_enable_intr = mvsata_pci_enable_intr;
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pci_aprint_devinfo(pa, "Marvell Serial-ATA Host Controller");
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/* Map I/O register */
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if (pci_mapreg_map(pa, PCI_MAPREG_START,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&psc->psc_iot, &psc->psc_ioh, NULL, &size) != 0) {
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aprint_error_dev(self, "can't map registers\n");
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return;
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}
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psc->psc_pc = pa->pa_pc;
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psc->psc_tag = pa->pa_tag;
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if (bus_space_subregion(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_HCARBITER_SPACE_OFFSET,
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size - MVSATA_PCI_HCARBITER_SPACE_OFFSET, &sc->sc_ioh)) {
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aprint_error_dev(self, "can't subregion registers\n");
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return;
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}
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sc->sc_iot = psc->psc_iot;
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/* Enable device */
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csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_MASTER_ENABLE;
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pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr);
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if (pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error_dev(self, "couldn't map interrupt\n");
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return;
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}
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intrstr = pci_intr_string(psc->psc_pc, intrhandle, intrbuf, sizeof(intrbuf));
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psc->psc_ih = pci_intr_establish_xname(psc->psc_pc, intrhandle, IPL_BIO,
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mvsata_pci_intr, sc, device_xname(self));
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if (psc->psc_ih == NULL) {
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aprint_error_dev(self, "couldn't establish interrupt\n");
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return;
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}
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aprint_normal_dev(self, "interrupting at %s\n",
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intrstr ? intrstr : "unknown interrupt");
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/*
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* Check if TWSI serial ROM initialization was triggered.
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* If so, then PRE/AMP configuration probably are set after
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* reset by serial ROM. If not then override the PRE/AMP
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* values.
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*/
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reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG);
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read_pre_amps = (reg & 0x00000001) ? 1 : 0;
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for (i = 0; i < __arraycount(mvsata_pci_products); i++)
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if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor &&
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PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model)
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break;
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KASSERT(i < __arraycount(mvsata_pci_products));
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rv = mvsata_attach(sc, &mvsata_pci_products[i],
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mvsata_pci_sreset, mvsata_pci_misc_reset, read_pre_amps);
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if (rv != 0) {
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pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
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return;
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}
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mask = MVSATA_PCI_MAINIRQ_PCI;
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for (hc = 0; hc < sc->sc_hc; hc++)
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for (port = 0; port < sc->sc_port; port++)
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mask |=
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MVSATA_PCI_MAINIRQ_SATAERR(hc, port) |
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MVSATA_PCI_MAINIRQ_SATADONE(hc, port);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK,
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mask);
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if (!pmf_device_register(self, NULL, mvsata_pci_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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static int
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mvsata_pci_detach(device_t self, int flags)
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{
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struct mvsata_pci_softc *psc = device_private(self);
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/* XXXX: needs reset ? */
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pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
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pmf_device_deregister(self);
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return 0;
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}
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static int
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mvsata_pci_intr(void *arg)
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{
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struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)arg;
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struct mvsata_softc *sc = &psc->psc_sc;
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uint32_t cause;
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int hc, port, handled = 0;
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cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_MAINIRQCAUSE);
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for (hc = 0; hc < sc->sc_hc; hc++)
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for (port = 0; port < sc->sc_port; port++)
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if (cause & MVSATA_PCI_MAINIRQ_SATAERR(hc, port)) {
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struct mvsata_port *mvport;
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mvport = sc->sc_hcs[hc].hc_ports[port];
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handled |= mvsata_error(mvport);
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}
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for (hc = 0; hc < sc->sc_hc; hc++)
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if (cause &
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(MVSATA_PCI_MAINIRQ_SATADONE(hc, 0) |
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MVSATA_PCI_MAINIRQ_SATADONE(hc, 1) |
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MVSATA_PCI_MAINIRQ_SATADONE(hc, 2) |
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MVSATA_PCI_MAINIRQ_SATADONE(hc, 3)))
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handled |= mvsata_intr(&sc->sc_hcs[hc]);
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if (cause & MVSATA_PCI_MAINIRQ_PCI) {
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uint32_t pe_cause;
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if (sc->sc_flags & MVSATA_FLAGS_PCIE) {
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pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_E_IRQCAUSE);
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aprint_error_dev(MVSATA_PCI_DEV(psc),
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"PCIe error: 0x%x\n", pe_cause);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_E_IRQCAUSE, ~pe_cause);
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} else {
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pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_IRQCAUSE);
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aprint_error_dev(MVSATA_PCI_DEV(psc),
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"PCI error: 0x%x\n", pe_cause);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_IRQCAUSE, ~pe_cause);
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}
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handled = 1; /* XXXXX */
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}
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return handled;
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}
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static bool
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mvsata_pci_resume(device_t dev, const pmf_qual_t *qual)
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{
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/* not yet... */
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return true;
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}
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static int
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mvsata_pci_sreset(struct mvsata_softc *sc)
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{
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struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc;
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uint32_t val;
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int i;
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS);
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val |= MVSATA_PCI_MAINCS_SPM;
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bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val);
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for (i = 0; i < 1000; i++) {
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delay(1);
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_MAINCS);
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if (val & MVSATA_PCI_MAINCS_PME)
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break;
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}
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if (!(val & MVSATA_PCI_MAINCS_PME)) {
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aprint_error_dev(MVSATA_PCI_DEV(psc),
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"PCI master won't flush\n");
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return -1;
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}
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/* reset */
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bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS,
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val | MVSATA_PCI_MAINCS_GSR);
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS);
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delay(5);
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if (!(val & MVSATA_PCI_MAINCS_GSR)) {
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aprint_error_dev(MVSATA_PCI_DEV(psc),
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"can't set global reset\n");
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return -1;
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}
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/* clear reset and *reenable the PCI master* (not mentioned in spec) */
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val &= ~(MVSATA_PCI_MAINCS_GSR | MVSATA_PCI_MAINCS_SPM);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val);
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS);
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delay(5);
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if (val & MVSATA_PCI_MAINCS_GSR) {
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aprint_error_dev(MVSATA_PCI_DEV(psc),
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"can't set global reset\n");
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return -1;
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}
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return 0;
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}
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static int
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mvsata_pci_misc_reset(struct mvsata_softc *sc)
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{
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struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc;
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#define MVSATA_PCI_COMMAND_DEFAULT 0x0107e371
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#define MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY 0x800003e0
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uint32_t val, pci_command = MVSATA_PCI_COMMAND_DEFAULT;
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bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_FLASHCTL,
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0x0fcfffff);
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if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) {
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_GPIOPORTCTL);
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val &= 0x3;
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#if 0
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val |= 0x00000060;
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#else /* XXXX */
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val |= 0x00000070;
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#endif
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_GPIOPORTCTL, val);
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}
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if (sc->sc_gen == gen1) {
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/* Expansion ROM BAR Enable */
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_EROMBAR);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_EROMBAR, val | 0x00000001);
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}
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if (sc->sc_flags & MVSATA_FLAGS_PCIE) {
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_MAINIRQMASK, 0);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_E_IRQCAUSE, 0);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_E_IRQMASK, 0);
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} else {
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val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
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MVSATA_PCI_MODE);
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bus_space_write_4(psc->psc_iot, psc->psc_ioh,
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|
MVSATA_PCI_MODE, val & 0xff00ffff);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_DISCTIMER, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_MSITRIGGER, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_XBARTIMEOUT, 0x000100ff);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_MAINIRQMASK, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_SERRMASK, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_IRQCAUSE, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_IRQMASK, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_ERRLOWADDR, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_ERRHIGHADDR, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_ERRATTRIBUTE, 0);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_ERRCOMMAND, 0);
|
|
}
|
|
|
|
/* Enable LED */
|
|
if (sc->sc_gen == gen1) {
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_GPIOPORTCTL, 0);
|
|
|
|
/* XXXX: 50xxB2 errata ? */
|
|
#if 0
|
|
if (sc->sc_rev == 3) {
|
|
int port;
|
|
|
|
val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_GPIOPORTCTL);
|
|
|
|
/* XXXX: check HDD connected */
|
|
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_GPIOPORTCTL, val);
|
|
}
|
|
#endif
|
|
|
|
/* Disable Flash controller clock */
|
|
val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_EROMBAR);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_EROMBAR, val & ~0x00000001);
|
|
} else
|
|
#if 0
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_GPIOPORTCTL, 0x00000060);
|
|
#else /* XXXX */
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_GPIOPORTCTL, 0x00000070);
|
|
#endif
|
|
|
|
if (sc->sc_flags & MVSATA_FLAGS_PCIE)
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_E_IRQMASK, 0x0000070a);
|
|
else {
|
|
val = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_MODE);
|
|
if ((val & 0x30) >> 4) { /* PCI-X */
|
|
int mv60x1b2 =
|
|
((sc->sc_model == PCI_PRODUCT_MARVELL_88SX6041 ||
|
|
sc->sc_model == PCI_PRODUCT_MARVELL_88SX6081) &&
|
|
sc->sc_rev == 7);
|
|
|
|
pci_command &=
|
|
~MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY;
|
|
if (sc->sc_gen == gen1 || mv60x1b2)
|
|
pci_command &=
|
|
~MVSATA_PCI_COMMAND_MWRITECOMBINE;
|
|
} else
|
|
if (sc->sc_gen == gen1)
|
|
pci_command &=
|
|
~(MVSATA_PCI_COMMAND_MWRITECOMBINE |
|
|
MVSATA_PCI_COMMAND_MREADCOMBINE);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_COMMAND, pci_command);
|
|
|
|
#define MVSATA_PCI_INTERRUPT_MASK 0x00d77fe6
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_SERRMASK, MVSATA_PCI_INTERRUPT_MASK);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_IRQMASK, MVSATA_PCI_INTERRUPT_MASK);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
mvsata_pci_enable_intr(struct mvsata_port *mvport, int on)
|
|
{
|
|
struct mvsata_pci_softc *psc =
|
|
device_private(mvport->port_ata_channel.ch_atac->atac_dev);
|
|
uint32_t mask;
|
|
int hc = mvport->port_hc->hc, port = mvport->port;
|
|
|
|
mask = bus_space_read_4(psc->psc_iot, psc->psc_ioh,
|
|
MVSATA_PCI_MAINIRQMASK);
|
|
if (on)
|
|
mask |= MVSATA_PCI_MAINIRQ_SATADONE(hc, port);
|
|
else
|
|
mask &= ~MVSATA_PCI_MAINIRQ_SATADONE(hc, port);
|
|
bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK,
|
|
mask);
|
|
}
|