421 lines
12 KiB
C
421 lines
12 KiB
C
/* $NetBSD: si.c,v 1.63 2009/11/21 04:16:52 rmind Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Adam Glass, David Jones, and Gordon W. Ross.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file contains only the machine-dependent parts of the
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* Sun3 SCSI driver. (Autoconfig stuff and DMA functions.)
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* The machine-independent parts are in ncr5380sbc.c
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*
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* Supported hardware includes:
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* Sun SCSI-3 on OBIO (Sun3/50,Sun3/60)
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* Sun SCSI-3 on VME (Sun3/160,Sun3/260)
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*
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* Could be made to support the Sun3/E if someone wanted to.
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*
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* Note: Both supported variants of the Sun SCSI-3 adapter have
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* some really unusual "features" for this driver to deal with,
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* generally related to the DMA engine. The OBIO variant will
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* ignore any attempt to write the FIFO count register while the
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* SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with
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* by setting the FIFO count early in COMMAND or MSG_IN phase.
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*
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* The VME variant has a bit to enable or disable the DMA engine,
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* but that bit also gates the interrupt line from the NCR5380!
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* Therefore, in order to get any interrupt from the 5380, (i.e.
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* for reselect) one must clear the DMA engine transfer count and
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* then enable DMA. This has the further complication that you
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* CAN NOT touch the NCR5380 while the DMA enable bit is set, so
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* we have to turn DMA back off before we even look at the 5380.
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*
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* What wonderfully whacky hardware this is!
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*
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* Credits, history:
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*
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* David Jones wrote the initial version of this module, which
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* included support for the VME adapter only. (no reselection).
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*
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* Gordon Ross added support for the OBIO adapter, and re-worked
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* both the VME and OBIO code to support disconnect/reselect.
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* (Required figuring out the hardware "features" noted above.)
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*
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* The autoconfiguration boilerplate came from Adam Glass.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: si.c,v 1.63 2009/11/21 04:16:52 rmind Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsipi_debug.h>
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#include <dev/scsipi/scsiconf.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/dvma.h>
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/* #define DEBUG XXX */
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#include <dev/ic/ncr5380reg.h>
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#include <dev/ic/ncr5380var.h>
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#include "sireg.h"
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#include "sivar.h"
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/*
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* Transfers smaller than this are done using PIO
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* (on assumption they're not worth DMA overhead)
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*/
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#define MIN_DMA_LEN 128
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int si_debug = 0;
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#ifdef DEBUG
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#endif
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/* How long to wait for DMA before declaring an error. */
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int si_dma_intr_timo = 500; /* ticks (sec. X 100) */
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static void si_minphys(struct buf *);
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/*
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* New-style autoconfig attachment. The cfattach
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* structures are in si_obio.c and si_vme.c
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*/
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void
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si_attach(struct si_softc *sc)
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{
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struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
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volatile struct si_regs *regs = sc->sc_regs;
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int i;
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/*
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* Support the "options" (config file flags).
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* Disconnect/reselect is a per-target mask.
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* Interrupts and DMA are per-controller.
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*/
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ncr_sc->sc_no_disconnect =
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(sc->sc_options & SI_NO_DISCONNECT);
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ncr_sc->sc_parity_disable =
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(sc->sc_options & SI_NO_PARITY_CHK) >> 8;
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if (sc->sc_options & SI_FORCE_POLLING)
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ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
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#if 1 /* XXX - Temporary */
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/* XXX - In case we think DMA is completely broken... */
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if (sc->sc_options & SI_DISABLE_DMA) {
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/* Override this function pointer. */
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ncr_sc->sc_dma_alloc = NULL;
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}
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#endif
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ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
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/*
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* Initialize fields used by the MI code
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*/
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ncr_sc->sci_r0 = ®s->sci.sci_r0;
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ncr_sc->sci_r1 = ®s->sci.sci_r1;
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ncr_sc->sci_r2 = ®s->sci.sci_r2;
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ncr_sc->sci_r3 = ®s->sci.sci_r3;
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ncr_sc->sci_r4 = ®s->sci.sci_r4;
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ncr_sc->sci_r5 = ®s->sci.sci_r5;
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ncr_sc->sci_r6 = ®s->sci.sci_r6;
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ncr_sc->sci_r7 = ®s->sci.sci_r7;
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ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
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/*
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* Allocate DMA handles.
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*/
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i = SCI_OPENINGS * sizeof(struct si_dma_handle);
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sc->sc_dma = (struct si_dma_handle *)
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malloc(i, M_DEVBUF, M_WAITOK);
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if (sc->sc_dma == NULL)
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panic("si: dvma_malloc failed");
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for (i = 0; i < SCI_OPENINGS; i++)
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sc->sc_dma[i].dh_flags = 0;
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ncr_sc->sc_channel.chan_id = 7;
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ncr_sc->sc_adapter.adapt_minphys = si_minphys;
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/*
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* Initialize si board itself.
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*/
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ncr5380_attach(ncr_sc);
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}
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static void
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si_minphys(struct buf *bp)
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{
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if (bp->b_bcount > MAX_DMA_LEN) {
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#ifdef DEBUG
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if (si_debug) {
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printf("%s len = 0x%x.\n", __func__, bp->b_bcount);
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Debugger();
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}
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#endif
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bp->b_bcount = MAX_DMA_LEN;
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}
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minphys(bp);
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}
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#define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
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SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR )
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int
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si_intr(void *arg)
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{
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struct si_softc *sc = arg;
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volatile struct si_regs *si = sc->sc_regs;
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int dma_error, claimed;
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u_short csr;
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claimed = 0;
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dma_error = 0;
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/* SBC interrupt? DMA interrupt? */
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csr = si->si_csr;
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NCR_TRACE("si_intr: csr=0x%x\n", csr);
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if (csr & SI_CSR_DMA_CONFLICT) {
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dma_error |= SI_CSR_DMA_CONFLICT;
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printf("%s: DMA conflict\n", __func__);
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}
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if (csr & SI_CSR_DMA_BUS_ERR) {
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dma_error |= SI_CSR_DMA_BUS_ERR;
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printf("%s: DMA bus error\n", __func__);
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}
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if (dma_error) {
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if (sc->ncr_sc.sc_state & NCR_DOINGDMA)
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sc->ncr_sc.sc_state |= NCR_ABORTING;
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/* Make sure we will call the main isr. */
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csr |= SI_CSR_DMA_IP;
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}
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if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
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claimed = ncr5380_intr(&sc->ncr_sc);
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#ifdef DEBUG
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if (!claimed) {
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printf("%s: spurious from SBC\n", __func__);
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if (si_debug & 4)
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Debugger(); /* XXX */
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}
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#endif
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/* Yes, we DID cause this interrupt. */
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claimed = 1;
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}
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return claimed;
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}
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/*****************************************************************
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* Common functions for DMA
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****************************************************************/
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/*
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* Allocate a DMA handle and put it in sc->sc_dma. Prepare
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* for DMA transfer. On the Sun3, this means mapping the buffer
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* into DVMA space. dvma_mapin() flushes the cache for us.
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*/
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void
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si_dma_alloc(struct ncr5380_softc *ncr_sc)
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{
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struct si_softc *sc = (struct si_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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struct scsipi_xfer *xs = sr->sr_xs;
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struct si_dma_handle *dh;
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int i, xlen;
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void *addr;
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#ifdef DIAGNOSTIC
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if (sr->sr_dma_hand != NULL)
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panic("%s: already have DMA handle", __func__);
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#endif
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addr = ncr_sc->sc_dataptr;
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xlen = ncr_sc->sc_datalen;
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/* If the DMA start addr is misaligned then do PIO */
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if (((vaddr_t)addr & 1) || (xlen & 1)) {
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printf("%s: misaligned.\n", __func__);
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return;
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}
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/* Make sure our caller checked sc_min_dma_len. */
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if (xlen < MIN_DMA_LEN)
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panic("%s: xlen=0x%x", __func__, xlen);
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/*
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* Never attempt single transfers of more than 63k, because
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* our count register may be only 16 bits (an OBIO adapter).
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* This should never happen since already bounded by minphys().
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* XXX - Should just segment these...
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*/
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if (xlen > MAX_DMA_LEN) {
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printf("%s: excessive xlen=0x%x\n", __func__, xlen);
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Debugger();
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ncr_sc->sc_datalen = xlen = MAX_DMA_LEN;
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}
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/* Find free DMA handle. Guaranteed to find one since we have
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as many DMA handles as the driver has processes. */
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for (i = 0; i < SCI_OPENINGS; i++) {
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if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
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goto found;
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}
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panic("si: no free DMA handles.");
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found:
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dh = &sc->sc_dma[i];
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dh->dh_flags = SIDH_BUSY;
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if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, addr, xlen, NULL,
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BUS_DMA_NOWAIT) != 0)
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panic("%s: can't load dmamap", device_xname(ncr_sc->sc_dev));
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dh->dh_dmaaddr = sc->sc_dmap->dm_segs[0].ds_addr;
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dh->dh_dmalen = xlen;
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/* Copy the "write" flag for convenience. */
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if (xs->xs_control & XS_CTL_DATA_OUT)
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dh->dh_flags |= SIDH_OUT;
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bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen,
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(dh->dh_flags & SIDH_OUT) == 0 ?
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BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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#if 0
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/*
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* Some machines might not need to remap B_PHYS buffers.
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* The sun3 does not map B_PHYS buffers into DVMA space,
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* (they are mapped into normal KV space) so on the sun3
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* we must always remap to a DVMA address here. Re-map is
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* cheap anyway, because it's done by segments, not pages.
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*/
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if (xs->bp && (xs->bp->b_flags & B_PHYS))
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dh->dh_flags |= SIDH_PHYS;
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#endif
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/* success */
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sr->sr_dma_hand = dh;
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return;
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}
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void
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si_dma_free(struct ncr5380_softc *ncr_sc)
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{
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struct si_softc *sc = (struct si_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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struct si_dma_handle *dh = sr->sr_dma_hand;
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#ifdef DIAGNOSTIC
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if (dh == NULL)
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panic("%s: no DMA handle", __func__);
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#endif
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if (ncr_sc->sc_state & NCR_DOINGDMA)
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panic("%s: free while in progress", __func__);
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if (dh->dh_flags & SIDH_BUSY) {
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bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen,
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(dh->dh_flags & SIDH_OUT) == 0 ?
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BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap);
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dh->dh_dmaaddr = 0;
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dh->dh_flags = 0;
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}
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sr->sr_dma_hand = NULL;
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}
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#define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
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SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)
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#define POLL_TIMO 50000 /* X100 = 5 sec. */
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/*
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* Poll (spin-wait) for DMA completion.
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* Called right after xx_dma_start(), and
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* xx_dma_stop() will be called next.
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* Same for either VME or OBIO.
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*/
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void
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si_dma_poll(struct ncr5380_softc *ncr_sc)
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{
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struct si_softc *sc = (struct si_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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volatile struct si_regs *si = sc->sc_regs;
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int tmo;
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/* Make sure DMA started successfully. */
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if (ncr_sc->sc_state & NCR_ABORTING)
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return;
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/*
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* XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here
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* XXX: (on obio) or even worse (on vme) a 10mS. delay!
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* XXX: I really doubt that is necessary...
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*/
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/* Wait for any "DMA complete" or error bits. */
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tmo = POLL_TIMO;
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for (;;) {
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if (si->si_csr & CSR_MASK)
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break;
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if (--tmo <= 0) {
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printf("si: DMA timeout (while polling)\n");
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/* Indicate timeout as MI code would. */
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sr->sr_flags |= SR_OVERDUE;
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break;
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}
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delay(100);
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}
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NCR_TRACE("si_dma_poll: waited %d\n",
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POLL_TIMO - tmo);
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#ifdef DEBUG
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if (si_debug & 2) {
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printf("%s: done, csr=0x%x\n", __func__, si->si_csr);
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}
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#endif
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}
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