144 lines
5.5 KiB
C
144 lines
5.5 KiB
C
/* $NetBSD: cgfourteenreg.h,v 1.7 2010/06/12 21:25:56 macallan Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University and
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* its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Register/dac/clut/cursor definitions for cgfourteen frame buffer
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*/
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/* Locations of control registers in cg14 register set */
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#define CG14_OFFSET_CURS 0x1000
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#define CG14_OFFSET_DAC 0x2000
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#define CG14_OFFSET_XLUT 0x3000
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#define CG14_OFFSET_CLUT1 0x4000
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#define CG14_OFFSET_CLUT2 0x5000
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#define CG14_OFFSET_CLUT3 0x6000
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#define CG14_OFFSET_CLUTINCR 0xf000
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/* cursor registers */
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#define CG14_CURSOR_PLANE0 0x1000
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#define CG14_CURSOR_PLANE1 0x1080
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#define CG14_CURSOR_CONTROL 0x1100
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#define CG14_CRSR_ENABLE 0x04
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#define CG14_CRSR_DBLBUFFER 0x02
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#define CG14_CURSOR_X 0x1104
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#define CG14_CURSOR_Y 0x1106
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#define CG14_CURSOR_COLOR1 0x1108
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#define CG14_CURSOR_COLOR2 0x110c
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#define CG14_CURSOR_COLOR3 0x1110
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/* ranges in framebuffer space */
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#define CG14_FB_VRAM 0x00000000
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#define CG14_FB_CBGR 0x01000000
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#define CG14_FB_PX32 0x03000000
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#define CG14_FB_PB32 0x03400000
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#define CG14_FB_PG32 0x03800000
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#define CG14_FB_PR32 0x03c00000
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/* Main control register set */
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struct cg14ctl {
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volatile uint8_t ctl_mctl; /* main control register */
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#define CG14_MCTL 0x00000000
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#define CG14_MCTL_ENABLEINTR 0x80 /* interrupts */
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#define CG14_MCTL_ENABLEVID 0x40 /* enable video */
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#define CG14_MCTL_PIXMODE_MASK 0x30
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#define CG14_MCTL_PIXMODE_8 0x00 /* data is 16 8-bit pixels */
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#define CG14_MCTL_PIXMODE_16 0x20 /* data is 8 16-bit pixels */
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#define CG14_MCTL_PIXMODE_32 0x30 /* data is 4 32-bit pixels */
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#define CG14_MCTL_PIXMODE_SHIFT 4
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#define CG14_MCTL_TMR 0x0c
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#define CG14_MCTL_ENABLETMR 0x02
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#define CG14_MCTL_rev0RESET 0x01
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#define CG14_MCTL_POWERCTL 0x01
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volatile uint8_t ctl_ppr; /* packed pixel register */
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volatile uint8_t ctl_tmsr0; /* test status reg. 0 */
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volatile uint8_t ctl_tmsr1; /* test status reg. 1 */
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volatile uint8_t ctl_msr; /* master status register */
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volatile uint8_t ctl_fsr; /* fault status register */
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volatile uint8_t ctl_rsr; /* revision status register */
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#define CG14_RSR_REVMASK 0xf0 /* mask to get revision */
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#define CG14_RSR_IMPLMASK 0x0f /* mask to get impl. code */
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volatile uint8_t ctl_ccr; /* clock control register */
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/* XXX etc. */
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};
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/* Hardware cursor map */
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#define CG14_CURS_SIZE 32
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struct cg14curs {
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volatile uint32_t curs_plane0[CG14_CURS_SIZE]; /* plane 0 */
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volatile uint32_t curs_plane1[CG14_CURS_SIZE];
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volatile uint8_t curs_ctl; /* control register */
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#define CG14_CURS_ENABLE 0x4
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#define CG14_CURS_DOUBLEBUFFER 0x2 /* use X-channel for curs */
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volatile uint8_t pad0[3];
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volatile uint16_t curs_x; /* x position */
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volatile uint16_t curs_y; /* y position */
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volatile uint32_t curs_color1; /* color register 1 */
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volatile uint32_t curs_color2; /* color register 2 */
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volatile uint32_t pad[444]; /* pad to 2KB boundary */
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volatile uint32_t curs_plane0incr[CG14_CURS_SIZE]; /* autoincr */
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volatile uint32_t curs_plane1incr[CG14_CURS_SIZE]; /* autoincr */
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};
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/* DAC */
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struct cg14dac {
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volatile uint8_t dac_addr; /* address register */
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volatile uint8_t pad0[255];
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volatile uint8_t dac_gammalut; /* gamma LUT */
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volatile uint8_t pad1[255];
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volatile uint8_t dac_regsel; /* register select */
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volatile uint8_t pad2[255];
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volatile uint8_t dac_mode; /* mode register */
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};
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#define CG14_CLUT_SIZE 256
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/* XLUT registers */
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struct cg14xlut {
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volatile uint8_t xlut_lut[CG14_CLUT_SIZE]; /* the LUT */
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volatile uint8_t xlut_lutd[CG14_CLUT_SIZE]; /* ??? */
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volatile uint8_t pad0[0x600];
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volatile uint8_t xlut_lutinc[CG14_CLUT_SIZE]; /* autoincrLUT*/
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volatile uint8_t xlut_lutincd[CG14_CLUT_SIZE];
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};
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/* Color Look-Up Table (CLUT) */
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struct cg14clut {
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volatile uint32_t clut_lut[CG14_CLUT_SIZE]; /* the LUT */
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volatile uint32_t clut_lutd[CG14_CLUT_SIZE]; /* ??? */
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volatile uint32_t clut_lutinc[CG14_CLUT_SIZE]; /* autoincr */
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volatile uint32_t clut_lutincd[CG14_CLUT_SIZE];
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};
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