/* Copyright (c) 1993 Adam Glass * Copyright (c) 1988 University of Utah. * Copyright (c) 1982, 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * the Systems Programming Group of the University of Utah Computer * Science Department. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: Utah $Hdr: cpu.h 1.16 91/03/25$ * * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91 * cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp */ #ifdef KERNEL /* * Exported definitions unique to sun3/68k cpu support. */ /* * definitions of cpu-dependent requirements * referenced in generic code */ #define COPY_SIGCODE /* copy sigcode above user stack in exec */ #define cpu_exec(p) /* nothing */ #define cpu_wait(p) /* nothing */ /* * Arguments to hardclock, softclock and gatherstats * encapsulate the previous machine state in an opaque * clockframe; for hp300, use just what the hardware * leaves on the stack. */ struct clockframe { int pc; int ps; }; #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) #define CLKF_PC(framep) ((framep)->pc) #define CLKF_INTR(framep) (0) /* XXX laziness */ typedef struct clockframe clockframe; /* * Preempt the current process if in interrupt from user mode, * or after the current trap/syscall if in system mode. */ #define need_resched() { want_resched++; aston(); } /* * Give a profiling tick to the current process from the softclock * interrupt. On hp300, request an ast to send us through trap(), * marking the proc as needing a profiling tick. */ #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston();} /* * Notify the current process (p) that it has a signal pending, * process as soon as possible. */ #define signotify(p) aston() #define aston() (astpending++) int astpending; /* need to trap before returning to user mode */ int want_resched; /* resched() was called */ #define fuswintr(x) (-1) #define suswintr(x,y) (-1) #include /* values for machineid */ #define CPU_ARCH_MASK 0xf0 #define SUN3_ARCH 0x10 #define SUN3_IMPL_MASK 0x0f #define SUN3_MACH_160 0x01 #define SUN3_MACH_50 0x02 #define SUN3_MACH_260 0x03 #define SUN3_MACH_110 0x04 #define SUN3_MACH_60 0x07 #define SUN3_MACH_E 0x08 extern int machineid, mmutype, ectype; extern char *intiobase, *intiolimit; /* 680X0 function codes */ #define FC_USERD 1 /* user data space */ #define FC_USERP 2 /* user program space */ #define FC_CONTROL 3 /* HPMMU: clear TLB entries */ #define FC_SUPERD 5 /* supervisor data space */ #define FC_SUPERP 6 /* supervisor program space */ #define FC_CPU 7 /* CPU space */ /* fields in the 68020 cache control register */ #define IC_ENABLE 0x0001 /* enable instruction cache */ #define IC_FREEZE 0x0002 /* freeze instruction cache */ #define IC_CE 0x0004 /* clear instruction cache entry */ #define IC_CLR 0x0008 /* clear entire instruction cache */ #define IC_CLEAR (IC_CLR|IC_ENABLE) #endif