.\"	$NetBSD: pci_configure_bus.9,v 1.14 2006/02/24 21:57:22 wiz Exp $
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.Dd February 21, 2006
.Dt PCI_CONFIGURE_BUS 9
.Os
.Sh NAME
.Nm pci_configure_bus ,
.Nm pci_conf_hook ,
.Nm pci_conf_interrupt
.Nd perform PCI bus configuration
.Sh SYNOPSIS
.In dev/pci/pciconf.h
.Ft int
.Fo pci_configure_bus
.Fa "pci_chipset_tag_t pc"
.Fa "struct extent *ioext"
.Fa "struct extent *memext"
.Fa "struct extent *pmemext"
.Fa "int firstbus"
.Fa "int cacheline_size"
.Fc
.Sh DESCRIPTION
The
.Fn pci_configure_bus
function configures a PCI bus for use.
This involves:
.Bl -bullet
.It
Defining bus numbers for all busses on the system,
.It
Setting the Base Address Registers for all devices,
.It
Setting up the interrupt line register for all devices,
.It
Configuring bus latency timers for all devices, and
.It
Configuring cacheline sizes for all devices.
.El
.Pp
In traditional PCs and Alpha systems, the BIOS or firmware takes care
of this task, but that is not the case for all systems.
.Fn pci_configure_bus
should be called prior to the autoconfiguration of the bus.
.Pp
The
.Fa pc
argument is a machine-dependent tag used to specify the PCI chipset to the
system.
This should be the same value used with
.Fn pci_make_tag .
The extent arguments
define memory extents from which the address space for the cards will be
taken.
These addresses should be in the PCI address space.
The
.Fa ioext
extent is for PCI I/O accesses.
The
.Fa memext
extent is for PCI memory accesses that might have side effects.
I.e., that can not be cached.
The
.Fa pmemext
extent is for PCI memory accesses that can be cached.
The
.Fa pmemext
extent will be used for any ROMs and any memory regions that are marked as
.Dq prefetchable
in their BAR.
If an implementation does not distinguish between
prefetchable and non-prefetchable memory, it may pass NULL for
.Fa pmemext .
In this case, prefetchable memory allocations will be made from the
non-prefetchable region.
The
.Fa firstbus
argument indicates the number of the first bus to be configured.
The
.Fa cacheline_size
argument is used to configure the PCI Cache Line Size Register; it
should be the size, in bytes, of the largest D-cache line on the system.
.Pp
An implementation may choose to not have full configuration performed
by
.Fn pci_configure_bus
on certain PCI devices, such as PCI host bridges or PCI bus analyzers
which are instantiated as devices on the bus.
In order for this to take place, the header
.Aq Pa machine/pci_machdep.h
must define the
.Dv __HAVE_PCI_CONF_HOOK
symbol (without a value), and a machine-dependent function
.Fn pci_conf_hook
(declared in the same header)
must be defined.
The prototype for this function is
.Pp
.Fn "int pci_conf_hook" "pci_chipset_tag_t pc" "int bus" \
    "int device" "int function" "pcireg_t id"
.Pp
In this function,
.Fa bus ,
.Fa device ,
and
.Fa function
uniquely identify the item being configured;
in addition to this, the value of the device's PCI identification
register is passed in
.Fa id .
For each device
.Fn pci_conf_hook
can then decide upon the amount of configuration to be performed by
returning a bitwise inclusive-or of the following flags:
.Bl -tag -width PCI_CONF_ENABLE_MEM -offset indent
.It Dv PCI_CONF_MAP_IO
Configure Base Address Registers that map I/O space
.It Dv PCI_CONF_MAP_MEM
Configure Base Address Registers that map memory space
.It Dv PCI_CONF_MAP_ROM
Configure Expansion ROM Base Address register
.It Dv PCI_CONF_ENABLE_IO
Enable I/O space accesses
.It Dv PCI_CONF_ENABLE_MEM
Enable memory space accesses
.It Dv PCI_CONF_ENABLE_BM
Enable bus mastering
.El
.Pp
In addition,
.Dv PCI_CONF_ALL
specifies all of the above.
.Pp
One of the functions of
.Fn pci_configure_bus
is to configure interrupt
.Dq line
information.
This must be done on a machine-dependent basis, so a
machine-dependent function
.Fn pci_conf_interrupt
must be defined.
The prototype for this function is
.Pp
.Fn "void pci_conf_interrupt" "pci_chipset_tag_t pc" "int bus" \
    "int device" "int pin" "int swiz" "int *iline"
.Pp
In this function,
.Fa bus ,
.Fa device ,
and
.Fa pin ,
uniquely identify the item being configured.
The
.Fa swiz
argument is a
.Dq swizzle ,
a sum of the device numbers of the primary interface of the bridges between
the host bridge and the current device.
The function is responsible for setting the value of
.Fa iline .
See chapter 9 of the
.Dq PCI-to-PCI Bridge Architecture Specification
for more information on swizzling (also known as interrupt routing).
.Sh RETURN VALUES
If successful
.Fn pci_configure_bus
returns 0.
A non-zero return value means that the bus was not completely
configured for some reason.
A description of the failure will be displayed on the console.
.Sh ENVIRONMENT
The
.Fn pci_configure_bus
function is only included in the kernel if the kernel is compiled with
the
.Dv PCI_NETBSD_CONFIGURE
option enabled.
.Sh EXAMPLES
The
.Fn pci_conf_hook
function in evbppc's walnut implementation looks like:
.Pp
.Bd -literal -compact
int
pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func,
    pcireg_t id)
{

	if ((PCI_VENDOR(id) == PCI_VENDOR_IBM \*[Am]\*[Am]
	     PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) ||
	    (PCI_VENDOR(id) == PCI_VENDOR_INTEL \*[Am]\*[Am]
	     PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) {
		/* Don't configure the bridge and PCI probe. */
		return 0;
	}
	return (PCI_CONF_ALL \*[Am] ~PCI_CONF_MAP_ROM);
}
.Ed
.Pp
The
.Fn pci_conf_interrupt
function in the sandpoint implementation looks like:
.Pp
.Bd -literal -compact
void
pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
    int swiz, int *iline)
{
	if (bus == 0) {
		*iline = dev;
	} else {
		*iline = 13 + ((swiz + dev + 3) \*[Am] 3);
	}
}
.Ed
.Pp
The BeBox has nearly 1GB of PCI I/O memory starting at processor address
0x81000000 (PCI I/O address 0x01000000), and nearly 1GB of PCI memory
starting at 0xC0000000 (PCI memory address 0x00000000).
The
.Fn pci_configure_bus
function might be called as follows:
.Pp
.Bd -literal -compact
	struct extent *ioext, *memext;
	...
	ioext  = extent_create("pciio",  0x01000000, 0x0fffffff, M_DEVBUF,
	    NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem", 0x00000000, 0x0fffffff, M_DEVBUF,
	    NULL, 0, EX_NOWAIT);
	...
	pci_configure_bus(0, ioext, memext, NULL);
	...
	extent_destroy(ioext);
	extent_destroy(memext);
	...
.Ed
.Pp
Note that this must be called before the PCI bus is attached during
autoconfiguration.
.Sh SEE ALSO
.Xr pci 4 ,
.Xr extent 9
.Sh HISTORY
.Fn pci_configure_bus
was added in
.Nx 1.6 .