changes made the usage here clash with the pool code, and the
pool code is overkill for this case (fixed number of elements,
always NOWAIT).
Use a simple static freelist allocator instead (pv_list-like).
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in the not-too-distant future.
cpu_idle() and new cpu_switch() to replace the old cpu_switch()
which did the lot. Runs leaner without overly blocking interrupts.
Includes cleanup of the RAS code to make use of callee-saved registers.
Benchmarks on DX4 @ 100MHz reveal a slight performance improvement
but probably not statistically signficant. More TBD to verify this.
Changes passed a pounding on Athlon @ 1GHz too.
This merge changes the device switch tables from static array to
dynamically generated by config(8).
- All device switches is defined as a constant structure in device drivers.
- The new grammer ``device-major'' is introduced to ``files''.
device-major <prefix> char <num> [block <num>] [<rules>]
- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.
- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.
- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.
- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.
- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
If a segment starts exactly at 16M don't try to split it because that causes
the code to try to call uvm_page_physload with a zero length segment.
(kern/17199)
bits of the K6 cache-control-register: disable the cache; flush the cache;
set the bits; re-enable the cache (all much like programming the pentium
mtrr's). See reference posted to tech-kern; also review there by thorpej.
