immediately with a lost interrupt on udma mode 2, downgrades to mode 1
at which point it silently corrupts data on high disk activity. This
happens on two out of 3 machines I own that exhibit high disk activity.
wdc drivers (like macppc's obio IDE interface) can use it. Also add
support to both wd attach line and to wdc_print_modes() to print
Ultra/{33,66,100} for respective UDMA modes (From Manuel Bouyer).
disable multiword DMA for these chips. multiword DMA can be forced with
options PCIIDE_AMD756_ENABLEDMA on rev D2 chips, but use at your own risk !
While I'm there remove a duplicate allocation of sc_wdcdev.nchannels in HPT
code.
Some AMD controllers have a bug which can look up the machine when using DMA, so
disable DMA for some revisions (info provided by AMD).
"options PCIIDE_AMD756_ENABLEDMA" can be used to force DMA on these chips.
<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>
also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.
the IRQ has been cleared on the drive.
- use pa->pa_class instead of re-reading PCI_CLASS_REG when possible
- Add support for Highpoint HPT366 and HPT370 (370 untested), based
on patches from Roger Brooks <R.S.Brooks@liverpool.ac.uk> posted on
current-users Mach, 15. Given how Highpoint docs have been wrong for the
366, the 370 is likely to not work.
Thanks to Chris Cappuccio <chris@dqc.org> for sending me the Highpoint
docs, and to Total Archive (http://www.totalarchive.com/) for sending
me hardware.
if an IRQ was not detected, unless the force flag was given. Use this to
detect if the IRQ was for us (closer to shared IRQ for controllers which
don't have their own IRQ handler in pciide.c) and to poll for DMA xfer.
Also makes the timeout recovery code simpler.
- ATAPI cleanup: don't call controller-specific functions from atapiconf.c
(wdc_*), so that it's possible to attach an atapibus to something else
than a wdc/pciide (Hi Lennart :).
Overload struct scsi_adapter with struct atapi_adapter, defined
as struct scsi_adapter + atapi-specific callbacks. scsipi_link still points
to an scsi_adapter, atapi code casts it to atapi_adapter if needed.
Move atapi_softc to atapiconf.h so that it can be used by the underlying
controller code (e.g. atapi_wdc.c).
Add an atapi-specific callback *atapi_probedev(), which probe a drive
in a controller-specific way, allocate the sc_link and fills in the
ataparams if needed. It then calls atapi_probedev() (from atapiconf.c)
to do the generic initialisations and attach the device.
- While I'm there merge and centralise the state definitions in atavar.h.
It should now be possible to use a common ata/atapi routine to set the
drive's modes (will do later).
"Don't enable UDMA modes for revisions of SiS 5513 < 0xd0
The only revisions I know which don't actually support UDMA are 0x09 and below..
But the only revision I know which does support UDMA is 0xd0 (and presumably
above that)"
chip-dependant code this required the following changes:
- Instead of attaching the device in a generic way with some chip-dependant
routines, use a chip-dependant attach routine with some common code
factored out. The code is marginally bigger, but this allows the CMD64x
flag hack to go away.
- For chips that report per-channel 'irq triggered', test this before calling
wdcintr() for the native-pci irq case (compat intr can't be shared),
as wdcintr() has no good way to know if a irq was for it or not, and
ends up with irq loss. XXX for chips that don't have this feature irq sharing
will not work properly !
- add my copyrigth notice (could have been done some time ago I think :)
There are still some issues to be solved with the Promise controller and
ATAPI devices.
Many thanks to Paul Newhouse for shipping me 2 Ultra/33 boards for doing this
work.
"If a channel has no drives, do *not* unmap its I/O regions.
It's not really safe to use them for anything else, and in legacy mode it
will just cause us to probe the channel again as an ISA device."
- keep the modes supported by the drive in struct ata_drive_datas (will be
later used for downgrading the DMA/PIO mode on error)
- use config flags to force/disable PIO/DMA/UDMA modes
- For the CMD PCI0643/6 setup DMA mode to DMA Read multiple.
eg the Cypress ISA bridge:
-put channel mapping into the chip specific part, unify with
channel_probe() into channel_map()
-use pointer to channel data as function call argument wherever possible
instead of the channel number
-allow the "compat" channel number to differ from the per-controller
channel number - for mapping and interrupt functions
-add support for SiS5598 and Cypress 82C693 chips
Mostly done by Manuel, I only contributed to the first 2 items.
Don't claim DMA support if we don't have explicit support for this chip.
They're to may way to loose when trying to use DMA without configuring the
controller and disks.
in the printing of DMA mode (piix3/4 only)
others: set the debug_mask to 0, so that debug messages are turned off by
default but can be easily turned on.
Reset drive_flags to 0 for unconfigured devices, so that they are ignored
later. For configured devices, reset state to 0 after probe/attach.
if i drive is responding):
-if the reset succeeds, check some registers to make sure there is really
a drive (and not a chipset which echoes back the last written value)
-explicitely select the master before trying to read the master's status
and see if anything responds. if nothing (that's attributable to the
PCI IDE controller) responds, then that channel either has no devices on
it or has been disabled (via a non-standard mechanism) by the BIOS. If nothing
responds, don't map the compat.-mode interrupt or attach the wdc to that
channel, because the BIOS is likely to assign that IRQ to a different PCI
device. If that happens, the kernel will panic because that device will
try to map the IRQ level-triggered, but the compat interrupt will have been
mapped edge-triggered. (One possible way around this is to map the compat
interrupt edge-triggered, but it's not clear reading the spec that this
is correct or desirable.)
insert a check to see whether a channel appears to be enabled. Shouldn't
be necessary, according to the spec, but some PC chipsets allow individual
compatibility channels to be disabled. "I hate PCs."
christos