In the new sljt version, ppc_cache_flush() is guarded by
SLJIT_CACHE_FLUSH_OWN_IMPL. We can keep is as long as we
don't define SLJIT_CACHE_FLUSH_OWN_IMPL.
guest requirements and support.
Add infrastructure to query the hypervisor about features support.
For verbose boot, print the features suppoted by the hypervisor for this
guest.
Changes since the last import:
r313 Fix a racing condition reported by Mozilla.
r312 Support Android ARM64 cacheflush. Patch by Tavian Barnes.
r311 Update opcode dump.
r310 Better type specification for integer operations and conditional types.
r309 Better type specification for long mul and divide operators.
r308 Better type specification for floating point operations.
r307 Change d and s postfixes to f64 and f32.
r306 Change b,h,i postifxes to 8,16,32.
r305 Fix a wrong immediate number. Reported by Michael McConville.
r304 Make file patch by Michael McConville.
r303 Landed changes created by Michael McConville.
r302 Add support for cmov on x86.
r301 Tile-Gx fixes by Walter Lee
r300 Add WinCE support.
r299 Add a tutorial for SLJIT. Contributed by Wen Xichang.
r298 Improve integer division.
r297 Start reworking the integer division.
r296 Add an overview for SLJIT.
r295 Small optimizations for x86 and ARM64.
r294 Fix ARM64 SP alignment.
r293 Add a new sljit_set_compiler_memory_error function.
r292 Add missing argument on ARM32.
r291 Minor fixes and NOINLINE support.
r290 Support custom memory allocators.
r289 Add SLJIT_DOUBLE_ALIGNMENT support and emit_op_custom size check.
r288 Add suport for SLJIT_ARGUMENT_CHECKS on all architectures.
r287 Add SLJIT_ARGUMENT_CHECKS compiler option and lots of cleanups.
r286 Support the new naming on PPC and MIPS.
r285 Support the new naming on ARM and SPARC.
r284 Move the type letter to the beggining of the floating point opcodes.
r283 Add i_ s_ d_ froms to compare types.
r282 Fix an incorrect form of mul on x86-64.
r281 Refactoring sljitConfigInternal.h header.
r280 Remove variable locals offset.
r279 Test skips are not reported if verbose is disabled.
r278 Add options to sljit_emit_enter and sljit_set_context.
r277 Reindexing opX opcodes.
r276 Some comments are fixed and minor refactors were done.
r275 Minor optimizations.
r274 Extend the register set on ARM.
r273 Extend the register set on PPC, MIPS, SPARC.
r272 Allow remapping of any registers: not just scratch->saved, but saved->scratch as well.
r271 Renaming floating point registers to support more of them.
r270 Extend the register set on x86.
r269 Renaming integer registers for preparing the support of any all machine registers.
r268 Refactor a macro to work when debug is disabled.
r267 Introduce architecture macros without 32/64 bit postfix.
r266 The floating point conversion operators are finished on PPC, and they are supported on all architectures now.
r265 FPU operations support locals access now. CONW is supported on PPC now.
r264 Continue code refactoring, MOVS/MOVD are optimized on all architectures.
r263 SPARC implementation of floating point operators.
r262 Small refactorings.
r261 MIPS implementation of floating point conversion operators.
r260 ARM implementation of floating point operators.
r259 x86 implementation of floating point conversion operators.
r258 Refactoring sljit_emit_fop1 opcodes, inserting placeholders for new ones.
- Enable debug messages but set log level to be quiet. Provide a
system (hw.iscsi.debug) to set the log level at run time.
- Replace old tsleep/wakeup synchronization with mutexes and condvars.
- Defer actions from callouts (basically timeouts) to the cleanup thread.
- Protect lists and unique ids with mutexes. protect connection usecount
by using atomic operations.
- Assert kernel lock when calling into scsipi and network code.
- Use this to make send/receive/cleanup threads MPSAFE.
- Fix handling of out-of-CCB/out-of-PDU conditions against the scsipi layer.
- Bump number of PDUs to 128 to avoid virtually all out-of-PDU conditions
- Make use of softc structure for attach/detach operations.
- Track open file handles to prevent detach when busy.
- Move some global variables to make them static.
- Fix 'Overlapping Commands Attempted' error by marking commands as
simply ordered (ATTR_SIMPLE) like FreeBSD.
fresh install in a dual boot scenario to fail. This is because fstab will be
referencing wd(4) and the kernel expecting dk(4).
Closes PR port-macppc/51160
it's not a 16750 either. Like the 16750 it has the IIR_BUSY interrupt,
which is triggered when writing to LCR while the chip
can't accept it. But unlike the 16750, it has a specific register,
HALT, to allow writing to the LCR and divisor registers, and then
commit the changes.
Tested on an A20 SoC, changing the baud rate while keeping the
tty device open and incoming data.
amd64 and i386.
The fillkpt loop is equivalent to the following:
do {
/* fill in the slot */
/* increment %ebx to the next slot */
/* increment %eax to the next pa */
} while (%ecx > 0)
The issue here is that if %ecx = 0 (i.e., the chunk we are trying to
map is zero-sized), there is still one entry created in the page table.
The kernel expects the va<->pa translation to be linear in low memory.
If there is a zero-sized chunk, the dead entry creates a +4096 offset in
the virtual space, with two consecutive entries that point to the same
physical address. In other words, the mappings are not linear anymore,
which causes the kernel to die.
Before my recent changes, there were only two big chunks that were
mapped, and neither of these could be zero-sized. Now, with multiple,
fine-grained chunks, it is possible that the [SYMS]+[PRELOADED_MODULES]
chunk could be zero-sized.
[PRELOADED_MODULES] is almost never here, and [SYMS] is always here on
default kernels. Except for floppies, where the bootloader does not load
[SYMS].
Should fix PR 51148.
as documented in sysctl(7):
0 - ptrace does not affect mprotect
1 - (default) mprotect is disabled for processes that start executing from
the debugger (being traced)
2 - mprotect restrictions are relaxed for traced processes
c450c13615f7af0673230041da4216b3de5bc4d3.patch
This patch fixes 2 issues in AccessWidth/BitOffset support and adds
comments to justify the BitOffset/BitWidth style macro usages. Lv Zheng.
This patch introduces ACPI_IS_ALIGNED() macro. Lv Zheng.
The old register descriptors are translated in AcpiTbInitGenericAddress()
with AccessWidth being filled with 0. This breaks code in
AcpiHwGetAccessBitWidth() when the registers are 16-bit IO ports and their
BitWidth fields are filled with 16. The rapid fix is meant to make code
written for AcpiHwGetAccessBitWidth() regression safer before the issue is
correctly fixed from AcpiTbInitGenericAddress(). Reported by
John Baldwin <jhb@freebsd.org>, Fixed by Lv Zheng <lv.zheng@intel.com>,
Tested by Jung-uk Kim <jkim@freebsd.org>.
pooka