The vnodes are always referenced on entry.
If we changed ulfs_remove() and ulfs_rmdir() to return the locked dvp
the vnodes were always locked on entry.
Remove an outdated comment from lfs_reserveavail(), unlocking/relocking
the vnode was removed in rev 1.49.
so widen it to 'long long'. pass2 uses it for the number of entries in
a directory (IIUC) which does not need to be wider than int, but for
now let's not try to split into two fields. FUTURE...
This is always uint32_t, but having a name for it both makes things
clearer and avoids confusion about whether it should be 32 or 64 bit.
Note: deployed in only one place (that was erroneously tagged
ondisk32) so far.
- compute the maximum file size using LFS_BLKPTRSIZE()
- use the new IINFO in pass 6 instead of uint32_t pointers
- use accessors to read and write indirect blocks
blocks portion of the segment summary.
A segment summary block begins with a header (SEGSUM); the rest of the
block contains FINFO structures describing file blocks growing upward
from the bottom (after the header), and IINFO structures describing
inode blocks grown downward from the end of the block. (When they meet
the segment is full regardless of how many blocks might be left.)
IINFO contains just a block number, and until now this information was
handled by just using uint32_t*; switching to a structure will make
the code a lot easier to read, and also make it easier to have 32-bit
and 64-bit versions without making a mess.
This commit just adds the structures and accessors; they'll be
deployed into the code in subsequent commits.
XXX: We don't have an event system so that we can issue callback that
will be run on construction or destruction to enable and disable probes
XXX: We don't have a way to use link_sets across modules properly.
to avoid the extra line. Now output looks like:
gpio0 at awingpio0 port B: 18 pins
gpio1 at awingpio0 port C: 25 pins
gpio2 at awingpio0 port D: 28 pins
gpio3 at awingpio0 port E: 12 pins
gpio4 at awingpio0 port G: 12 pins
gpio5 at awingpio0 port H: 28 pins
gpio6 at awingpio0 port I: 22 pins
what port is connected to what gpio instance:
gpio0 at awingpio0: 18 pins
gpio0: port B
gpio1 at awingpio0: 25 pins
gpio1: port C
gpio2 at awingpio0: 28 pins
gpio2: port D
gpio3 at awingpio0: 12 pins
gpio3: port E
gpio4 at awingpio0: 12 pins
gpio4: port G
gpio5 at awingpio0: 28 pins
gpio5: port H
gpio6 at awingpio0: 22 pins
gpio6: port I
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific
