Turns out genfb_softc must be at the start of its own device_private,
so we can't have it in the middle of a structure, and certainly can't
have potentially multiple genfbs per graphics device. Failing to do
this is why entering ddb didn't work with an i915drmkms console.
Instead of putting a genfb_softc into each drm_fb_helper, put a
device_t into each drm_fb_helper and create a new intelfb(4) device
for each Intel framebuffer. This will be more flexible, too, in case
we want accelerated framebuffers later on. (XXX Need to adapt the
radeon code, which I'm disabling until that happens to avoid breaking
the build.)
While here, defer disabling VGA, vga_cndetach, and genfb_attach until
we're actually ready to do them all together along with the mode
switch. This should reduce the amount of time during which the
screen is blanked, in case it hangs.
Format time_t by casting to intmax_t and using PRIdMAX, since we have
no PRIxyz for time_t.
We already hold the irq lock on entry to i915_record_ring_state, so
don't take it again.
ddev->dev is the actual device_t, and we need it for firmware load.
&pdev->dev is a dummy structure that serves no purpose except some
kludge in our Linux PCI compatibility crap. In Linux the two should
be the same, so no need to #ifdef __NetBSD__ this.
Linux's Documentation/atomic_ops.txt says in no uncertain terms these
must return 0 or 1, not zero or nonzero. I don't think this has
caused an issue for drm (yet), but better to have it right.
Trying to make do with Linux's page allocation interface is pretty
much always wrong: either we let uvm allocate pages in uvm objects
for us, or we use bus_dma.
Screen blanks on boot on the Ivy Bridge system with
DRM error in cpt_serr_int_handler: PCH transcoder A FIFO underrun
But after that everything is OK. Appears to be an upstream problem.
To investigate...
I think there's a cache flushing issue somewhere -- there are little
display artefacts on my T60.
del_timer_sync does not actually destroy the timer so it can't be
reused again -- but Linux has no routine to do that. So we'll have
to add that in where appropriate.
The changes since the last import are:
r257: Add missing ADJUST_LOCAL_OFFSET for ARM64.
r256: Move incorrectly placed array definitions.
r255: More work on testing environment.
r254: Refactor test default output.
r253: Pass entry adress in r12 on PPC-LE.
r252: Optimize calls on MIPS-64.
r251: Several minor fixes.
r250: Add missing SLJIT_IS_FPU_AVAILABLE checks and reorder U and S flags.
r249: Optimize jumps on ARM-64.
r248: Optimize jumps on PowerPC.
r247: MIPS64 support is mostly finished.
r246: MIPS arithmetic.
r245: Start working on MIPS64.
r244: Uniform names for TILE-Gx.
r243: Uniform the names of ARM compilers.
r242: Change ll to l on x86 and rename some instructions on ARM-64.
r241: Improved memory access in PPC and reordering the parameter type flags.
r240: Prepare for more registers on ARM-Thumb2 and renaming TMP_REGISTER to TMP_REG1 on x86.
r239: Prepare for more registers on ARMv5.
r238: Prepare for more registers on TILE-Gx.
r237: Prepare for more registers on MIPS and SPARC.
r236: Prepare for more registers on PPC.
r235: Prepare for more registers on x86.
r234: Most tests are pass on ARM-64 now.
r233: Around 25 test cases are now pass on ARM-64.
r232: More progress on ARM-64 and Thumb2 refactoring.
r231: Some progress an ARM-64 and ARM-T2 refactoring.
r230: Thumb2 code refactoring.
r229: Start working on ARM-64.
r228: Little endian PowerPC systems are supported now by the JIT compiler.
r227: TileGX architecture is now supported. Patch made by Jiong Wang.
r226: Cache flush for android. Patch by Giuseppe D'Angelo.
r225: Add support for forcibly freeing unused executable memory. Inspired by Carsten Klein.
r224: Few typo fixes.
r223: Reorder madvise and posix_madvise.
r222: The missing sljit_get_float_register_index function is added.
r221: Remove an invalid shift on ARM.
r220: JIT compiler now supports 32 bit Macs thanks to Lawrence Velazquez.
r219: Better code size statistics.
r218: Improvements for x86 and LIR dump.
r217: ICC and SunPro C fixes
r216: A new file for tracking internal changes are added.
r215: Less GNU dependnet Makefile and Intel style assemby for x86-64 systems.
r214: Switch from stdcall to cdecl in x86-32.
r213: Upstreaming minor fixes. Thanks for Daniel Richard G.
r212: Documentation update and a fix for a locking issue.
r211: Renaming temporaries to scratches to match the new name of the register. Does not affect compatibility.
r210: Improving assertions.
r209: Port sljit to SunPro C compiler. Patch by Daniel Richard G.
r208: SLJIT_TEMPORARY_REGx registers are renamed to SLJIT_SCRATCH_REGx.
r207: Removing unused checks.
r206: Optimizations for arm.
r205: Some optimizations on powerpc, mips and sparc.
r204: Rename sljit_emit_cond_value to sljit_emit_op_flags.
r203: Small x86 optimization.
r202: Finish cond_value with AND and INT_OP.
r201: More x86 fixes and improvements.
r200: Rename buf and code to inst.
r199: Replacing constants with instruction names in x86. Greatly improves maintainability.
r198: Only xmm0-xmm5 is volatile on Win64, so xmm6 must be saved.
r197: PowerPC shift right always modifies the carry flag. We may need to restore it.
r196: Rename SLJIT_F* functions to SLJIT_*D
r195: SLJIT_INT_OP works in the same way as SLJIT_SINGLE_OP: the input register arguments must be generated by the output of another instruction with SLJIT_INT_OP flag
r194: Renaming sljit_w to sljit_sw, sljit_i to sljit_si, sljit_h to sljit_sh, and sljit_b to sljit_sb.
r193: ARM single precision support.
r192: Single precision support added for ppc, mips and sparc.
r191: Add single precision support. Only works on x86 now.
r190: Relace C types with sljit types. No functionality change.
r189: Change 0 to NULL for mmap.
r188: Support environments where MAP_ANON is not available.
r187: Adding type descriptors for pointers and doubles (preparing for x32 ABIs and single precision support).
- Replace ipintrq and ip6intrq with the pktqueue mechanism.
- Eliminate kernel-lock from ipintr() and ip6intr().
- Some preparation work to push softnet_lock out of ipintr().
Discussed on tech-net.
This will do until I work out the twisty maze of registers, all
different, to reliably determine the size of the GTT (and hence the
GPU's virtual address space) separately from the size of the AGP
aperture.
- Fix sense of subtraction in i915_gem_restore_gtt_mappings (not
currently used, so this was harmless).
- Program gtt->gtt_scratch_map->dm_segs[0].ds_addr rather than
gtt->gtt_scratch_seg.ds_addr into the GTT for consistency with the
bus_dma API. These are currently the same, but if we ever start
using x86 iommu perhaps that may change.
- Kassert that the scratch PTE decodes into the scratch address.
Do transfer the GEM object reference to the uvm_aobj reference --
these are not the same thing. (There's another uvm object whose
references are the same thing as the GEM object references, but
that's not the uao.)
With these changes, it looks like the GPU is no longer trying to draw
graphics all over kernel data structures. Wish I had that month of
debugging back!
XXX Doing the check here is wrong; it serves only to report an
earlier problem, which is that there's on way to express constraints
on paddrs to uvm_obj_wirepages. bus_dmamem_alloc can do this, but it
gives us pages out of thin air, not pages backing a uvm object. I
was hoping this wouldn't manifest as a real problem, but evidently it
does.
- Fix order of subtraction in drm_mmap_paddr_locked.
- Address GEM objects' pages from 0, not from the mmap cookie.
- Check page alignment earlier in mmap code paths.
- Sprinkle kasserts throughout.
Still doesn't fix the garbage that is sometimes being scribbled all
over kernel memory!
riastradh