Commit Graph

11 Commits

Author SHA1 Message Date
yamt
ec5a93183a merge yamt-uio_vmspace branch.
- use vmspace rather than proc or lwp where appropriate.
  the latter is more natural to specify an address space.
  (and less likely to be abused for random purposes.)
- fix a swdmover race.
2006-03-01 12:38:10 +00:00
christos
95e1ffb156 merge ktrace-lwp. 2005-12-11 12:16:03 +00:00
matt
a6db24a485 Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create).  dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.
2005-03-09 19:04:43 +00:00
fvdl
7dd7f8baa2 Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.
2003-06-15 23:08:53 +00:00
kent
cd7d9faeaf Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it. 2003-01-28 01:07:51 +00:00
simonb
a85e214bda Make sure that private DMA flags don't overlap with standard DMA flags;
start these at 0x10000 to leave room for an increase in the latter.
2002-03-17 21:45:06 +00:00
thorpej
af66038f73 Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
2001-11-14 18:15:10 +00:00
thorpej
81bcece4d4 Implement bus_space_mmap(). 2001-09-04 16:32:42 +00:00
thorpej
babefc5331 Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.
2001-07-19 15:32:10 +00:00
enami
299159546d s/Alpha/MIPS/ in comment. 2001-05-31 02:20:55 +00:00
thorpej
16b9c60621 A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU).  There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.
2001-05-28 16:22:13 +00:00