Commit Graph

8 Commits

Author SHA1 Message Date
augustss
aaf6178285 Handle the "aligment" fault generated by DCBZ when the cache is off.
That way you can run the processor with caches off.
2002-05-19 06:35:45 +00:00
kleink
543f1e7a2d Handle the 601's Run Mode/Trace Exception as well. 2002-02-22 13:51:40 +00:00
simonb
18b2f7e6a1 Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
 - New pmap and revised trap handler.
 - Support on-chip timers, PCI controller, UARTs
 - Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
 - Add in-kernel PPC floating point emulation
 - New in{,4}_cksum that is between 1.5 and 5 times faster than the
   old version depending on CPU type.
General changes:
 - Kernel support for generic dbsym-style symbols.
2001-06-13 06:01:44 +00:00
tsubai
11b48d8a4d Thermal Management Interrupt is available on 750, too. 2000-11-20 15:16:04 +00:00
matt
95a8447ccf Add G4 specific exceptions (include AltiVec). 2000-11-19 20:48:20 +00:00
is
8a6db88c1d Prepare for AmigaPPC. 2000-05-25 21:10:14 +00:00
danw
6c14ba0dba Fill in the alignment trap handler a bit: now it can fix unaligned
floating point loads and stores (to work around a gcc bug), but will
still cause a bus error on other sorts of unaligned accesses.
2000-01-19 03:30:12 +00:00
ws
5804d3f648 PowerPC port 1996-09-30 16:34:14 +00:00