canonicalise several of the ipf option segments in various files
(this mostly means adding commented out IPFILTER_DEFAULT_BLOCK,
or adding commented or uncommented IPFILTER_LOG or IPFILTER_LOOKUP
option statements.)
i built about 20 of these kernels to check, but not all of them.
on the amount of physical memory and limited by NMBCLUSTERS if present.
Architectures without direct mapping also limit it based on the kmem_map
size, which is used as backing store. On i386 and ARM, the maximum KVA
used for mbuf clusters is limited to 64MB by default.
The old default limits and limits based on GATEWAY have been removed.
key_registered_sb_max is hard-wired to a value derived from 2048
clusters.
- renamed to MEMORY_DISK_RBFLAGS to better fit the rest of the
MEMORY_DISK options(4)
- change default value to RB_AUTOBOOT instead of RB_SINGLE, and adapt
the config(5) files accordingly
- document this option inside options(4)
See also http://mail-index.netbsd.org/tech-kern/2008/12/25/msg003924.html
Reviewed by abs@ in private mail.
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:
Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
them in the mi "files" file, and remove include statements from md files.
These shouldn't pull in additional kernel code when not in use, so it
shouldn't do any harm except a risk of namespace collisions which
should be easy to fix.
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.
Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.
Yank __HAVE_PMAP_PHYSSEG from all the oea code.
Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.
Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.
In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].
With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.
Please note, this is a port of 32bit ofppc, not a powerpc64 port.
Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.
Summary of changes:
Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
the call to pci_configure_bus(9) and it's supporting code is
copied verbatim from the prep port.
this allows us to completely remove the really gross pegasos
specific pegasospci_indirect_attach_hook() that set various
pci command regs, since all those devices (mostly work now,
see below) and additionally PCI plugin cards work now too.
it also makes the pegasos onboard vr(4) ethernet work with
disk boot (it previously only worked with netboot.)
in the generic macppc ofw pci conf hook and for pegasos,
don't configure the viaide(4) device, and don't configure
memory space on the fwohci(4) device.
with this, and my other recent ofppc/ppc changes the pegasos
port is mostly functional. the marvell gige is not working,
and my 512mb appears as only about 256mb, but otherwise
this port is almost done!
USB works fine. IEEE1394 is untested. Audio doesn't work (playing white noise).
Need to set IO/MEM-enable for IEEE1394 and audio, as the firmware (Smart
Firmware 1.2) doesn't do it.
Patch approved by Tim Rightnour.
- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
better on ofppc. In doing so, we also move a few functions around in
macppc and the generic ofw powerpc stuff to allow better sharing of code.
Also, introduce a model_init function.
move ofb_cons.c from macppc/dev to powerpc/oea and rename it to rascons.
This gets rid of some naming confusion, and makes it OFW-MI rather than
macppc specific.
Remove the ofb driver. I'm not interested in trying to make this work.
It should be replaced with the genfb driver, which I have added,
commented out because that driver needs work before it will function on
ofppc. (it's too panic-happy, and ofppc needs a working autoconf.c)
Change the way we do isa_inb/outb. The new way is a slightly nastier
hack, but won't run afoul of the other isa drivers as much.
Fix ofw_consinit.c to remove the dependency on ofb.
Write a complete OF boot console into ofw_consinit.c and rewire a bunch
of the ifdef logic in that file to use it when appropriate on both macppc
and ofppc. Get rid of the attempt to wire up the serial console early,
as that is extremely difficult on ofppc. Yank all the console code out
of ofppc/machdep.c. (This is a boot console only, not a full blown
console like ofcons.c)
Delete all the ofbus references out of the config files, and pull in
dev/ofw/openfirmio.c and dev/ofw/ofw_subr.c directly rather than pulling
in files.ofw. It might be worth going back and adding a files.ofw-nobus
to that directory to allow pulling in the openfirmware driver without
pulling in the whole ofbus mess.
Change rtas driver to connect directly to mainbus, like the PCI bus nodes do.
SEMMNI, SEMMNS, SEMUME and SHMMAXPGS.
They can be tweaked via sysctl now. Ports that were setting values on
them weren't touched, I only removed the ones that were commented out.
working properly. This is still a work in progress, and all work so far
has been based on the PegasosII machne.
1) Rewrite how the ISA memory and IO space maps are found. More work
will still need to be done in this area.
2) Add a new OFW method of pci configuration. So far I can only get this
to work on the primary PCI bus on the Pegasos. Unsure if this is a
pegasos bug or a code bug.
3) Add the rtas device to ofppc, and add an "rtas_reboot" function to
rtas to allow me to reboot the PegasosII. The rtas driver works, and is
a great start but needs to be changed slightly to allow easier access to
the functions from outside the driver.
4) Fix a number of bugs that existed in the shared PCI code for ofw that
probably weren't tickled by macppc.
There is much much more left to do here, this is all still a work in
progress, but this commit will allow other people to play around with the
code if they want to.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
kiyohara