XXX due to 2008-01-17 '10 gigabit Chelsio cards now compile and work, although
XXX not very well yet' commit this looks like having worked in past, but since
XXX ~2010 received only mechanical updates, and currently it's unreferenced
XXX and uncompilable - does it make sense to keep the driver around?
upon code inspection, remove intr re-establish from ath_pci_resume() -
not needed to re-establish interrupt there, no other driver does this,
and very likely it would actually fail nowadays
1. sets needs to be fixed
2. need to decide if I am going to add engine.so.MAJOR or use engine.so
like OpenSSL wants
3. padlock is MD (x86) needs asm to be added, and conditionally built
*) Timing vulnerability in DSA signature generation
The OpenSSL DSA signature algorithm has been shown to be vulnerable to a
timing side channel attack. An attacker could use variations in the signing
algorithm to recover the private key.
This issue was reported to OpenSSL on 16th October 2018 by Samuel Weiser.
(CVE-2018-0734)
[Paul Dale]
*) Timing vulnerability in ECDSA signature generation
The OpenSSL ECDSA signature algorithm has been shown to be vulnerable to a
timing side channel attack. An attacker could use variations in the signing
algorithm to recover the private key.
This issue was reported to OpenSSL on 25th October 2018 by Samuel Weiser.
(CVE-2018-0735)
[Paul Dale]
*) Added EVP_PKEY_ECDH_KDF_X9_63 and ecdh_KDF_X9_63() as replacements for
the EVP_PKEY_ECDH_KDF_X9_62 KDF type and ECDH_KDF_X9_62(). The old names
are retained for backwards compatibility.
[Antoine Salon]
*) Fixed the issue that RAND_add()/RAND_seed() silently discards random input
if its length exceeds 4096 bytes. The limit has been raised to a buffer size
of two gigabytes and the error handling improved.
This issue was reported to OpenSSL by Dr. Falko Strenzke. It has been
categorized as a normal bug, not a security issue, because the DRBG reseeds
automatically and is fully functional even without additional randomness
provided by the application.
ahci_intr_port() in form suitable for interrupt hanlder, and probe for GHC
MRSM flag as courtesy for use by the intr hook
towards multi-vector MSI/MSI-X support
Motivated by picocom checking for the existance of these at compile
time, and therefor previously not being able able to use picocom to
access the consoles of modern Rockchip SoCs (for example RK3399) running
at B1500000.
