like pm_kernel_cpus. Remove unecessary intersection with kcpuset_running.
Do not reset tp_userpmap if pmap_kernel().
- Remove pmap_tlb_mailbox_t wrapping, which is pointless after recent changes.
- pmap_tlb_invalidate, pmap_tlb_intr: constify for packet structure.
kcpuset(9) and thus replace hardcoded CPU bitmasks. This removes the
limitation of maximum CPUs.
- Support up to 256 CPUs on amd64 architecture by default.
Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.
CR0_WP (write protection bit) early on boot. Although it is set later via
cpu_init(), this can help tracking down invalid writes to pages mapped
as read only from ring 0.
No regression observed when booting under anita (QEMU) or a P4 host.
Depending on your hardware or setup, you may trigger code paths I have
overlooked. So if your machine does not start properly, or you get
page faults early during boot, please report them to me.
Amiga-style clockports. Also add a1k2cp(4) backend driver and the first
clockport device driver com_ss, that supports com(4) on clockport(4)
(particurarly Individual Computers SilverSurfer). Disabled by default,
since probe procedure is not written yet.
1.27 and 1.32. This will unbreak the build.
XXX The amdtemp device currently does not seem to provide correct sensor
values.
XXX The amdnb_misc device does not currently have a rescan capability, so
the amdtemp module will not instantiate any devices (PR kern/45268
reappears).
XXX The agp attachment at the same pci device and function (which was
the motivation for attaching amdtemp at pchb) probably ought to also
be moved to attach at amdnb_miscbus.
reporting differently. Each cpu and device interrupt gets its own
counter.
revision 1.14
Fix counting of interrupts for devices that attach to elroy(4). Shared
interrupts would be counted double, once for the interrupting device and
once for the device at the head of the chain. The handlers would run properly
though. Avoid this by giving each device its own interrupt counter instead
of using the counter provided by the generic interrupt handling code for the
head of the chain.
revision 1.13
Stop calling shared interrupt handlers as soon as one of them return 1
(positive interrupt was for me), like we do on other architectures.
This is done here, at the elroy(4) driver level, since this is where shared
PCI interrupts are handled. We could do something similar for dino(4) but
this optimization is probably not very relevant there.
This allows us to have independent drivers on the same device (northbridge f3)
each coming with a certain functionality/feature.
This way we do not need to mess with amdtemp(4) to utilize other features.
