Commit Graph

175 Commits

Author SHA1 Message Date
riastradh
03fc4aab4b Simplify bcm2835, tegra, and am335x hardware RNG drivers.
Tested by nick@.
2016-12-17 15:24:35 +00:00
maya
1b6aaa82cd Fix regression introduced by myself with the addition of da_fb_linebytes
tegra_fb was not adjusted so da_fb_linebytes was used uninitialized

add tfa_fb_linebytes and match radeonfb/nouveaufb code in how we set it
switch to using an initializer to hopefully avoid future errors

this change doesn't need to be pulled up, as tegra_fb.c is absent
in netbsd-7
2016-12-17 12:11:38 +00:00
ozaki-r
61f9115f54 Sweep unnecessary xcall.h inclusions 2016-11-21 04:10:05 +00:00
jakllsch
51c3cbc4f9 Add register definitions that will be necessary for future
tegraxusbpadctl(4) changes.
2016-09-26 20:08:58 +00:00
jakllsch
85627b239f Add xhci(4) attachment glue and firmware handler for Tegra K1 "XUSB"
xHCI controller.  Adjustments to tegraxusbpad(4) will be needed
to connect the controller to actual USB ports.
2016-09-26 20:05:03 +00:00
jakllsch
c5afe8e1ed Add Tegra124 CAR bits to support the XUSB xHCI core. 2016-09-08 00:38:23 +00:00
jakllsch
6178df370f Source of pll_p_out5 is not div_pllp_out5 but div_pll_p_out5. 2016-09-02 19:06:58 +00:00
jakllsch
0ec59b6319 Complete implementation of clocks for SPI controllers in tegra124_car. 2016-08-17 19:08:18 +00:00
jakllsch
33332c25ae Change tegra_pcie_conf_hook() to only give us the defaults without
enabled bus mastering.  Previously both bus mastering and ROM decode
were enabled at pci_configure_bus() time.  Both bus mastering and ROM
decode potentially have undesireable side effects.  These can best be
managed by drivers familiar with their hardware.
2016-08-17 00:22:56 +00:00
jakllsch
3574628685 Fix I2C clock calculations. Previously I2C clocks were half what was
requested.  The I2C clock registers have a LSB of one-half rather than
one-whole like the rest of them.
2016-08-17 00:09:19 +00:00
jakllsch
ca3490347b Send repeated start after command phase if there is any data phase
transfer, not just if the data phase a read operation.
2016-08-08 14:40:57 +00:00
jakllsch
062b43e2c7 Adjust data pointer using current, rather than upcoming, transfer length. 2016-08-08 14:36:56 +00:00
jmcneill
84e0ecfe04 IST_MPSAFE is not a valid flag for fdtbus_intr_establish; use
FDT_INTR_MPSAFE instead.
2016-05-23 18:21:14 +00:00
skrll
4e8e66439e Merge nick-nhusb
- API / infrastructure changes to support memory management changes.
- Memory management improvements and bug fixes.
- HCDs should now be MP safe
- conversion to KERNHIST based debug
- FS/LS isoc support on ehci(4).
- conversion to kmem(9)
- Some USB 3 support - mostly from Takahiro HAYASHI (t-hash).
- interrupt transfers now get proper DMA operations
- general bug fixes
    - kern/48308
    - uhub status notification improvements
    - umass(4) probe fix (applied to HEAD already)
    - ohci(4) short transfer fix
2016-04-23 10:15:27 +00:00
skrll
dc4391d06a Restore HOST1X and AHB_A2 to pmap_devmap to give pmap less work to do 2016-03-26 09:07:31 +00:00
skrll
3e98a566a4 G/C old structs 2016-03-26 08:42:07 +00:00
christos
f415d76a88 PR/50963: David Binderman: Use kmem_zalloc() so all members are initialized. 2016-03-13 17:38:44 +00:00
skrll
2a81ae4e13 Use the nvidia,has-utmi-pad-registers property.
From Jared.
2016-03-08 07:49:20 +00:00
chs
2f02870f3b zero the i2c_attach_args structure before filling it in.
fixes occasional crashes in iic_attach().
2016-02-14 19:54:19 +00:00
riastradh
461b4ecf4d Always initialize error.
Found by joerg.
2016-01-30 00:00:56 +00:00
marty
5cba62781b FDT: Interrupts -- add support for interrupt maps
The mct on exynos uses an interrupt map so we add support now.  Devices
represent their interrupts either through a combination of interrupt-parent
and interrupts properties, where the 'interrupts' property is an array of
one or more interrupt specifiers; or through a combination of an
interrupt-parent that points to an interrupt-map, where the interrupt-map
contains 2 or more entries consisting of an index, a pointer to an
interrupt-controller, and a specifier for that controller.

This code adds the ability to walk the interrupt-map and return a specifier.
Unfortunately, the addition requires changing the interface to the
interrupt-controllers' _establish and _intstr functions, so this check in
contains a rototill of the three existing fdt interrupt controllers to use
the new interface.
2016-01-05 21:53:48 +00:00
jmcneill
cf0b2cc745 use "watchdog" clock if not defined in fdt 2015-12-24 12:47:38 +00:00
jmcneill
07ee0d855d HDAUDIO_FLAG_NO_STREAM_RESET hack no longer required 2015-12-23 12:44:06 +00:00
jmcneill
65ddbe033a fix divider calculations for hdmi, and treat clock ID 211 as pll_p_out0 instead of directly pll_p 2015-12-23 12:43:25 +00:00
jmcneill
72ca8a5122 explicitly set high cursor/winbuf address bits when setting modes 2015-12-23 11:58:10 +00:00
jmcneill
1a623fc2e7 Add fdtbus_gpio_{read,write}_raw, which tells the controller not to take
polarity into account. Tegra GPIO pin data includes pin polarity, but so
does a regulator-fixed node, so the end result was that the enable value
was being swapped twice. Change fregulator to use the raw APIs, and adapt
Tegra and Exynos GPIO drivers to support this flag.
2015-12-22 22:19:07 +00:00
jmcneill
bf3831f489 tegra_car_* and tegra_i2c_dvc_write are no more 2015-12-22 22:12:08 +00:00
jmcneill
93e0bfeb6c Switch Tegra over to fdt based clocks and reset controls. 2015-12-22 22:10:36 +00:00
jmcneill
4e8cdc22f8 use of_getprop_uint32 2015-12-16 19:46:55 +00:00
jmcneill
a2676611ae fdtbus_gpio_read handles pin polarity, so fix inverted test in tegra_sdhc_card_detect 2015-12-15 15:33:19 +00:00
jmcneill
f724ec7be8 handle GPIO_ACTIVE_LOW flag 2015-12-14 20:57:34 +00:00
jmcneill
95d7e08adb Get rid of board-specific options. 2015-12-13 22:55:05 +00:00
jmcneill
36dcd298ce attach nouveau to fdt 2015-12-13 22:05:52 +00:00
jmcneill
e0ffebf2fd remove tegraio 2015-12-13 21:24:06 +00:00
jmcneill
d59db8d057 Use fdt for device enumeration. 2015-12-13 17:39:19 +00:00
jmcneill
0faea1444b replace 2292MHz entry with 2316MHz 2015-12-01 22:08:13 +00:00
jmcneill
a5c784b329 replace inline mc_read/write with MC_READ/WRITE macros, install intr handler with IST_MPSAFE flag 2015-11-22 12:26:11 +00:00
jmcneill
0af3fdefa2 Add SOC_THERM temperature sensor driver:
# envstat -d tegrasoctherm0
        Current  CritMax  WarnMax  WarnMin  CritMin  Unit
CPU0:    27.500                                      degC
CPU1:    27.500                                      degC
CPU2:    29.500                                      degC
CPU3:    29.000                                      degC
MEM0:    26.500                                      degC
MEM1:    27.000                                      degC
 GPU:    27.000                                      degC
PLLX:    28.000                                      degC
2015-11-21 22:55:32 +00:00
jmcneill
e7f77e44de Apply initial fuse offset in tegra_fuse_read instead of in each reg def 2015-11-21 22:52:31 +00:00
jakllsch
77011a5640 Add error interrupt handler to for Tegra MC. 2015-11-21 16:50:29 +00:00
jakllsch
81bc32ac74 Add a bunch of hopefully-useful Tegra MC register bits. 2015-11-21 16:48:33 +00:00
jmcneill
b2b0f53c9f Add FUSE driver, use it to determine maximum CPU frequency for the board.
Retire CPUFREQ_BOOT option and always use highest available CPU frequency.
2015-11-21 12:09:39 +00:00
jmcneill
ce4ce06889 aprint_verbose_dev -> aprint_debug_dev 2015-11-19 22:26:48 +00:00
jmcneill
2dce92d18e Remove HOST1X and AHB_A2 from pmap_devmap 2015-11-19 22:09:16 +00:00
jakllsch
8c719f5f2b Note the interrupt for Tegra MC in the locators list. 2015-11-18 17:12:06 +00:00
jakllsch
009c795f13 Complete the interrupt definitions list from the Tertiary Interrupt
Controller range of the Tegra K1.
2015-11-18 17:01:39 +00:00
jakllsch
1f4f07e05b Add PCI Extended Configuration support for tegrapcie(4).
Similar to the acpimcfg code, this only maps the extended configuration
space into KVA for known busses.
2015-11-17 22:01:39 +00:00
jakllsch
bd3ae4e6bc Do not clear the PCIe interrupt until we've allowed its cause to become
deasserted.  This halves the PCIe interrupt rate.
2015-11-17 00:08:33 +00:00
jmcneill
bd7b975898 initialize allocated gem object memory to 0 2015-11-16 21:41:29 +00:00
jmcneill
99ca455981 commit window changes when updating base 2015-11-16 21:14:51 +00:00