Commit Graph

10 Commits

Author SHA1 Message Date
christos
95e1ffb156 merge ktrace-lwp. 2005-12-11 12:16:03 +00:00
perry
f31bd063e9 nuke trailing whitespace 2005-02-27 00:26:58 +00:00
briggs
f5218aad0f Move the definition of NIDEDMA_TABLES from pciidereg.h to be closer to
its only user in pciide_common.c.  Also redefine NIDEDMA_TABLES to match
the max DMA transfer size specified in the call to bus_dmamap_create()
(IDEDMA_BYTE_COUNT_MAX instead of MAXPHYS).
The macro is also redefined to handle devices that have a PAGE_SIZE greater
than sc_dma_maxsegsz (buggy revision of satalink 3112 on ibm4xx).
2005-02-15 03:18:22 +00:00
fvdl
6242a54566 There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.

To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.

	bus_space_write_4(tag, handle, offset, value)

becomes

	bus_space_write_4(tag, handles[offset], 0, value)

Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-27 23:02:40 +00:00
thorpej
cfe0892ed3 NBPG -> PAGE_SIZE 2000-11-14 18:42:55 +00:00
soren
c70220f2a2 Move PCIIDE_CHANNEL_NAME macro to pciidereg.h. 2000-03-09 20:26:31 +00:00
bouyer
ca240ca7b5 Support for Acerlab M5229 IDE controller. Thanks to Thilo Manske for testing
the code, and to Takahiro Kambe who run several tests and finally found the
bug by himself :)
1999-02-02 16:13:59 +00:00
bouyer
19fddaeeb5 Merge bouyer-ide 1998-10-12 16:09:10 +00:00
cgd
0078e4bcd0 add def'ns for PCI IDE bus-master DMA interface recognition and register
mapping.
1998-03-04 19:17:10 +00:00
cgd
b37b33d302 PCI IDE glue. Right now, just glues 'wdc's to PCI IDE controller
channels.  Eventually should do things like support PCI IDE DMA (it _DOES
NOT_ do that now).
1998-03-04 06:35:11 +00:00