residual with the pnpbus probes, than it is to do it with raw isa probes,
so I've replaced the isa mkclock and mcclock code with a pnpbus attachment.
While writing the mkclock code, I realized that on motorola prep machines
the mkclock uses the same port range as the nvram part. (it's actually
the same chip/part). This was causing the nvram not to work on those
machines. Now the nvram code will recognize this, and wire up the
mkclock as well. The mkclock probe is just a stub probe used to
pre-detect the fact that this is one of those machines.
clear MIPS_SR_INT_IE in struct clockframe status to prevent
unintentional spllowersoftclock(9) in hardclock(9).
This may be required because current CLKF_BASEPRI() implementation
of NetBSD/arc doesn't check ICU_MASK and all ISA devices share
the same MIPS CPU INT2 interrupt.
BTW, has anyone tried IPL_ICU_MASK on any mips ports?
compiled in. Many TSC's out there are sensitive to cpu frequency
changes. On these platforms we need to use other fixed frequency
timers (e. g. ACPI_PM_TIMER). Maybe we should add detection code
here whether TSC is sensible to cpu frequency changes.
everytime softintr_schedule() is called. They don't have the same semantics
when called multiple times before the callback is triggered.
Should avoid huge numbers of si_callbacks being created when a machine is
overloaded.
XXX the fix certainly applies to the atari port, too.
1) Rather than build an array of the pci->intr mappings, build a proplib
tree.
2) add a SIMPLEQ of device properties to the pci_chipset_tag to hold the
proplib trees of each bus.
3) Move the interrupt routing code from pci_conf_interrupt to pci_map_intr()
4) Deal properly with non-native PCI bridge chips that are not recognized
by the prep firmware, and therefore are not noted in the residual data.
The major win of this restructure is #4. Hopefully I haven't broken
anything. Tested on a 7248-100, 7043-140 and 7024-E20.
New HAL includes some driver changes to register accesses.
Adds support for WLAN devices on AR5312 family devices.
Adds support 32-bit SPARC ath devices (untested).
ath enabled in SPARC64 GENERIC builds.
This HAL is tested and known to work for i386 PCI devices, SPARC64 PCI devices,
and AR5312 WiSoC devices. MIPS PCI devices appear to be busted (possibly only
on Alchemy hardware, unconfirmed), and cardbus support is untested due to
lack of test hardware.
Please report any new problems with this import to garrett@.
