that anyone installs over HIPPI either. On the other hand, lots of people
would like to be able to install over their wireless networks or with their
Tigon Gig-E cards: so, let's synchronize this file's contents with the
modern world (at least a little bit).
Note that we really need to decide whether, as they used to be, the INSTALL
config files will be GENERIC with some lines *deleted* or whether they will
be GENERIC with some lines commented out. Using both styles is bad, but I
haven't fixed it in this commit.
contain information suitable for allowing other parts of the kernel
to determine if a memory region is aligned to the largest data cache
line size present in the system.
Add a mips_dcache_compute_align() function which must be called whenever
one of the data cache line size variables is changed, in order to
compute mips_dcache_align and mips_dcache_align_mask.
Refuse to clear the modified bit on a page if it has a writeable kernel
mapping. I'm not sure this is the right thing to do, but since further
writes to the page won't set the bit again, it's safer than clearing it,
and makes NFS writes work properly.
Add debugging code for modified-bit emulation, which checksums
allegedly-unmodified pages to see if they're _really_ unmodified.
Disabled by default because it's slow.
In the process, fix a bug in pv_release whereby the modified bit for a
page got cleared when its last mapping was removed. This seems to finish
the NFS write fixes started by the first change above.
- correct trm_clock_period[] value
- pass BUS_DMA_{READ,WRITE,STREAMING} to bus_dmamap_load() as appropriate
- make sure to call bus_dmamap_unload() even after request sense
- saved srb params on request sense do not seem to be used,
so remove them from struct trm_srb
- handle target status more properly in trm_srb_done() and no need
to handle error retry in lower driver layer
- fix some comments
XXX Maybe need more cleanup around TQING for MI SCSI callback..
DMA register offsets, as well as IRQ, to children. Use direct
config. Use machine type/subtype to determine which devices are
present.
* Add support for the second SCSI controller on the Indigo2.
the controller/SCSI bus.
* Implement controller/SCSI bus reset on SGI HPC3 SCSI using the
"channel reset" bit in the SCSI DMA channel control register.
enami