to pci_attach_args. The latter is allocated on the stack during auto-
configuration and so will not be valid after that time.
It's amazing how the old code worked for so long. I guess pci_attach_args
is allocated deep in pid#0's kernel stack on most platforms.
- if_bcereg.h should only have register definitions, so declarations
of softc structure etc. should be in if_bce.c.
- The types of DMA descriptors should be u_int32_t, not unsigned long.
- netinet headers are not required here.
- Values passed via bce_tx_ring should also be byte-swapped.
- byte-swapping is not needed for bus_space access.
from me:
- KNF
- mark all magic numbers with /* MAGIC */ so they can be identified at
some point. there are 33 in total though many appear to be the same
value, or related (eg, the 6 emac points.)
leaves these issues:
- RX pre-packet headers need to be byte-swapped or not?
- PAGE_SIZE bytes are allocated for both TX and RX DMA ring descriptors,
but they should be 1024 (== sizeof(struct bce_dma_slot) * N[TR]XDESC).
- the mcast filter.
The driver backend is capable of supporting also ISA cards (no DMA)
and primary rate (PRI) cards in addition to the basic rate ones,
but I don't any to test on right now, so we don't support those
currently.
This code was originally written by Juha-Matti Liukkonen <jml@cubical.fi>
of Cubical Solutions Ltd. for FreeBSD, and was ported to NetBSD by
myself for the same company.
CCB is returned to the caller.
- Make code paths that can use twe_ccb_alloc_wait() use it, and assert
that a CCB is always returned from that function.
- Assert that a CCB is always returned when allocating the reserved CCB
for an AEN fetch.
reserved CCB. This means that all remaining callers of twe_param_get*()
are called from a valid thread context, and thus have no need to use a
reserved CCB. This will allow for further cleanup in a future commit.
1) Don't wait for DRQ on an IDENTIFY command -- if it's not set when we see
BSY clear, abort the command and ignore the drive. (Do this by testing
for DRQ in the read/write cases in __wdccommand_intr().)
2) Don't wait for DRQ to deassert when we finish an IDENTIFY (or any other
non-block command that reads data) -- we don't do this for block I/O, and
empirically it doesn't clear on my CF cards at all, causing a pointless 1s
delay.
3) Add comments to some of the delay()s, and add missing ones in wdcreset()
and the WDCC_RECAL in the so-called "pre-ATA" probe.
4) Slightly simplify the reset sequence -- we were doing an extra I/O.
5) Modify the register writability test to make sure that registers are not
overlapped -- this can happen in some weird cases with a missing device 1.
6) Check the error register value after the reset -- if it's not 01h or 81h,
as appropriate (see ATA spec), punt.
Tested with a number of ATA-only, ATAPI-only, mixed ATA-ATAPI, CF, and IDE
disk configurations.
Also remove the SINGLE_DRIVE nonsense again.
- Make AENs use the generic code table stuff.
- Add a few more AEN codes (from FreeBSD).
- Correct the context of a few AEN codes (some were listed as
"unit context" when they're really "port context").
- Add a queue of AENs that management tools in userspace can poll
(from FreeBSD).
most polling.
2) Clean up some goofiness in pciide -- get rid of the whole "candisable" path
(it's gratuitous) and simplify the code by calling pciide_map_compat_intr(),
*_set_modes() and wdc_print_modes() from central locations.
3) Add a register writability and register ghost test to eliminate phantom
drives more quickly.
This wasn't an error, on this chipset we have the SATA controller on function
0 of the IDE controller, not the pcib bridge.
Fix provided by Stephen Degler.
