Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.
particule device. In doing this, make a new the bpf_stat structure with
members that are u_long rather than u_int, matching the counters in the bpf_d.
the original bpf_stat is now bpf_stat_old and so to the original ioctl
is preserved as BIOCGSTATSOLD.
this fixes PR#25014. i386 GENERIC can re-enable PERFCTRS by default now
(it was disabled with x86 SMP support was commited to the trunk.)
XXX: should add P4 support
XXX: should add MP support
not a read operation should be allowed to sleep. This allows the use of
bd_rtout with a value of "-1" to be eliminated (signed comparison and
assignment to an unsigned long.)
* in 1.91, a change was introduced that had bpfpoll() returning POLLRDNORM
set when the timeout expired. This impacted poorly on performance as well
as causing select to return an fd available for reading when it wasn't.
Change the behaviour here to only allow the possibility of POLLIN being
returned as active in the event of a timeout.
the PCIX bus start to get heavily loaded. This only happen when using
chained descriptors, therefore work-around it by providing a private
pool of receive buffers able to contain a full-sized packet.
in tsleep()/wakeup() to appease gcc. Otherwise, the ch_flags value may
be cached in a register in atabus_thread(), and when it sets the WDCF_TH_RUN
bit after tsleep() it may loose loose the changes made by an interrupt handler
or another thread.
Problem analysed by Jukka Andberg on tech-kern.
otherwise an interrupt vector using a task gate (ie. ddbipi) messes it up.
- defer LDTR loading as well as cr3.
- tweak comments to make three copies of switching code more synchronized.
- Fix jumbo frame support.
- Disable interrupts at the chip in sip_intr().
- Disable checksum offloading if MTU > 8109 - the hardware is broken
in this case.
- Use the interrupt hold-off timer.
- Correct the Tx FIFO size.
- Add Pause Control/Status register definitions.
matt