Commit Graph

35 Commits

Author SHA1 Message Date
christos
d84c286204 expose the kernel types for standalone code. 2016-01-23 22:31:19 +00:00
christos
4d497c90e6 Hide {p,v}{addr,size}_t and register_t (and a couple more types that
are machine-specific) from userland unless _KERNEL/_KMEMUSER and a
new _KERNTYPES variables is defined. The _KERNTYPES should be fixed
for many subsystems that should not be using it (rump)...
2016-01-23 21:22:13 +00:00
martin
76713fa86f We never exec(2) with a kernel vmspace, so do not test for that, but instead
KASSERT() that we don't.
When calculating the load address for the interpreter (e.g. ld.elf_so),
we need to take into account wether the exec'd process will run with
topdown memory or bottom up. We can not use the current vmspace's flags
to test for that, as this happens too early. Luckily the execpack already
knows what the new state will be later, so instead of testing the current
vmspace, pass the info as additional argument to struct emul
e_vm_default_addr.
Fix all such functions and adopt all callers.
2015-11-26 13:15:34 +00:00
christos
5020ab68d5 Provide access to pc/sp/syscall-return registers like we have for mcontext 2015-09-15 15:49:02 +00:00
pooka
01d7ebdd80 Fix PTHREAD_FOO_INITIALIZER for C++ by not using volatile in the relevant
pthread types in C++ builds, attempt 2.

The problem with attempt 1 was making assumptions of what the MD
__cpu_simple_lock_t (declared volatile) looks like.  To get a same type
except non-volatile, we change the MD type to __cpu_simple_lock_nv_t
and typedef __cpu_simple_lock_t as a volatile __cpu_simple_lock_nv_t.
IMO, __cpu_simple_lock_t should not be volatile at all, but changing it
now is too risky.

Fixes at least Rumprun w/ gcc 5.1/5.2.  Furthermore, the mpd application
(and possibly others) will no longer require NetBSD-specific patches.

Tested: build.sh for i386, Rumprun for x86_64 w/ gcc 5.2.

Based on the patch from Christos in lib/49989.
2015-08-27 12:30:50 +00:00
uebayasi
ce93b3da57 Don't mention stab and DWARF sections, because these (poorly mtaintained)
lists only help to make them harder to read.

If those sections are found in inputs, they simply appear in outputs as
orphaned sections, sorted by section types and attributes.
2015-08-24 08:13:07 +00:00
uebayasi
6ecada7d3b .rel/.rela should not be generated in kernels. 2015-08-22 23:49:54 +00:00
uebayasi
220951d1d4 I bet setting search-directory for ld.so is useless in any kernel. 2015-08-21 02:35:52 +00:00
uebayasi
185745d477 Indent with 2 spaces. 2015-08-20 07:00:48 +00:00
maxv
02aebf5ed4 Remove KMEMSTATS. 2015-08-07 13:53:28 +00:00
matt
b0c9504248 Move the riscv lock.h which uses only compiler builtin atomic primitives
to a common location which can be used by others and make riscv's lock.h
use it.
2015-06-26 14:27:35 +00:00
matt
4bbed57554 Fix c&p error. 2015-06-26 14:20:11 +00:00
matt
8501aed0c2 add ELF64_MACHDEP_ID 2015-05-28 02:19:05 +00:00
matt
e4264474cf Add two new relocs for compressed branches. 2015-04-01 21:59:01 +00:00
matt
aa2d5871fd Add _REG_S0 2015-04-01 21:55:33 +00:00
matt
6691eaf9c2 _KMEMUSER only needs struct cpu_info 2015-04-01 21:55:03 +00:00
matt
ea4911da8a Accept the one instruction penalty and just use PTR_LA instead of doing
the relocs ourselves.
2015-03-31 11:53:13 +00:00
matt
16946e2051 Fix botch on putting user stack pointer into trapframe. 2015-03-31 11:48:10 +00:00
matt
1a68694ee8 Optimize the exception handle a little bit more. 2015-03-31 06:47:47 +00:00
matt
5539e041c8 Since there is only "scratch" system register for use on exception, come
up with a new scheme for its use.  Use PTR_LA, INT_S/INT_L, etc.  Disable
interrupts when returning from exceptions.  Use L_CPU(tp) to get the curcpu
pointer.

When the cpu gets an exception from kernel mode, the sscratch register will be
0 and curlwp will be in the "tp" register.  When the cpu gets an exception from
user mode, the sscratch register will be a pointer to the current lwp.

When an exception happends, the sp is atomically swapped with the sscratch
register.

	If the sp is zero, the exception was a kernel exception and the
	kernel exception path is taken: sp and sscratch are swapped again
	so sscratch is zero again and then a trapframe is allocated from
	the kernel stack.  The t1 register is saved and then the pre-trapframe
	sp is written to the trapframe.

	If sp was non-zero, the exception was from user mode.  The tp register
	is temporarily saved in L_MD_TP(sp) and sp is moved tp.  tp now
	contains a pointer to the current lwp.  A pointer to the user
	trapframe is loaded from L_MD_UTF(tp).  Then t1 is saved in the
	trapframe so it can be used.  The old sp is fetched from sscratch
	while sscratch is zeroed (indicated kernel mode).  The old sp is
	saved in the trapframe.

	Upon exiting the exception, if the exception is returning to user
	mode, the contents of tp is written to sscratch.
2015-03-31 01:30:50 +00:00
matt
234a34a18b Get curcpu() from L_CPU(tp) 2015-03-31 01:15:26 +00:00
matt
8b1d38bd25 Use sfence.vm instruction and change ptbr cse to sptbr csr 2015-03-31 01:14:57 +00:00
matt
c81fbb027b No more fatc (replaced by sfence.vm instruction). 2015-03-31 01:14:02 +00:00
matt
71a690b876 Add L_MD_TP 2015-03-31 01:12:47 +00:00
matt
9a7b236e49 Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the trapframe.
2015-03-31 01:12:29 +00:00
matt
e12d196579 Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the "tp"
(thread pointer) register.
2015-03-31 01:11:41 +00:00
matt
fb7a20f006 Use -mcmodel=medany to get PICish code. 2015-03-31 01:05:52 +00:00
matt
7eca982344 Use C11 atomic builtins instead of __asm. 2015-03-29 09:43:26 +00:00
matt
9687a165dd Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile.  This is mostly preliminary
waiting for the supervisor specification to come out.  Lots of missing pieces
but it mostly builds.
2015-03-28 16:13:56 +00:00
matt
f78f67fde4 Fix one error and make life for ld.elf_so a little easier. 2015-03-27 23:26:14 +00:00
matt
9d6a1448cc Switch to new ABI (return values now in a0/a1; v0/v1 are no more) 2015-03-27 06:57:21 +00:00
dennis
ca2461272f Shave an instruction from the generated code for the 32 bit byte
swap inline.  Prune 5 or 9 instructions (depending on what you count)
from the 64 bit byte swap inline.
2014-10-28 20:25:36 +00:00
dennis
08bd07a048 Correct 32 and 64 bit byte swap inlines. 2014-10-28 19:46:18 +00:00
dennis
7a9009c7b5 Fix a typo: the PC is likely in _REG_PC 2014-10-24 01:08:07 +00:00
matt
6cf6fe02a9 New files for Userland support of UCB RISC-V (both 32-bit and 64-bit) 2014-09-19 17:36:24 +00:00