Commit Graph

2 Commits

Author SHA1 Message Date
thorpej ce66bf0803 Rewrite the interrupt handling code:
- Compute the number of CPU pipeline cycles per second using the
  mc146818.
- Use the COMPARE interrupt for the hardclock interrupt.
- Collapse all interrupt priorities into a single priority, and use
  the CPU interrupt inputs to determine the interrupt source (local
  device, PCI device, ISA device, etc.)

This allows us to have interrupt sharing.
2001-06-10 05:26:58 +00:00
thorpej 16b9c60621 A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU).  There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.
2001-05-28 16:22:13 +00:00