to deal with aliasing of regular memory pages, because many processors don't
support it.
Now, the pmap marks all mappings of a page that has any non-equivalent
aliasing and any writable mapping, and the fault handlers watch for this
and flush other mappings out of the TLB and cache before (re)entering a
conflicting mapping.
When a page has non-equivalent aliasing, only one writable mapping at
a time may be in the TLB and cache. If no writable mapping is in the
TLB and cache, any number of read-only mappings may be.
The PA7100LC/PA7300LC fault handlers have not been converted yet.
fredette