arguments, so that a device can tell if its memory and I/O spaces are
enabled. The flags are cleared, depending on the contents of devices CSR
registers, in the machine-independent PCI bus code.
define CPU options and FIX_UNALIGNED_VAX_FP as header-generating options.
add pci_swiz_*_common.c when appropriate.
clean up a bit and sort more carefully.
Fixes broken blitting from rcons.
* Put back old 4.4bsd range test on cursor movement. 1.2 code is broken.
* Disable screensaver, it reportedly never comes back on properly.
Change in the way receive buffer areas are handled. Before we gave
the chip 16 buffers, each 1536 bytes (big enough for one packet).
Now we're handing the chip 8 buffers, each 4 Kbytes, and letting
the chip fit as many packets as it can in each one. This should
help keep it from running out of buffer space. Also make some of
the performance-crucial routines inline. It made no measurable
difference except to make me feel better
Changes from Bob Nestor <rnestor@metronet.com> to get closer to support
for his Apple SONIC-based nubus card.
Changes from me to try to get SONIC's MAC address from MacOS settings if
we can't read the PROM space.
this code makes equal sense for memory and I/O space, prefer to map
the PCI front end via memory space (conditionalized on a patchable kernel
variable), and do a bit of other random NetBSD-specific cleanup. (These
changes were sent to Justin Gibbs on March 28.)
mappings to a user pmap when it's created rather than at context
allocation time. Also, do not copy the kernel's region administration
to every user pmap, especially since no memory appears to be allocated
to copy it into.
As a result of this, we must now switch to context 0 in both pmap_copy_page()
and pmap_zero_page() (XXX).
* When a delayed write buffer falls off the LRU queue, arrange for it to go on
the AGE queue after being flushed out to disk.
* When a delayed write buffer is synced, leave it in its relative position in
the LRU queue.
cgd