in the CPUID instruction description in the "Intel Extended Memory 64
Technology Software Developer's Guide, Volume 1 of 2" available at
ftp://download.intel.com/technology/64bitextensions/30083402.pdf
This presently consists of the SYSCALL/SYSRET and the EM64T features.
CPUs with the EM64T feature available should be able to run amd64 code.
Reviewed by fvdl
* Get rid of PTmap, PTD, PTDpde, APTmap, APTD, and APTDpde from locore.S.
* Rename PTDpaddr to PDPpaddr, ptdpaddr in struct cpu_kcore_hdr to pdppaddr for consistency.
width implementation was a rather poor choice. Per discussion with
Charles Hannum.
Note: While this is technically an ABI change I believe it is a
change that we can afford at this time (and to be pulled up to
2.0). The types are not widely used yet, and a survey of pkgsrc
has not shown uses that would be adversely affected by it.
Michael Eriksson posted to port-i386 on 20031102, with various
modifications by me to work in the new sysctl(9) framework.
The code is enabled with 'options ENHANCED_SPEEDSTEP', and if
the CPU supports EST the following sysctl(8) nodes appear
(with the values that a Dell Inspiron 8600 + WUXGA with a
1.4GHz Pentium M CPU supports):
machdep.est.cpu_brand = Intel(R) Pentium(R) M processor 1400MHz
machdep.est.frequency.target = 1400
machdep.est.frequency.current = 1400
machdep.est.frequency.available = 1400 1200 1000 800 600
If EST support isn't available, the "machdep.est" sysctl sub-MIB
is not created.
Once we have a more general "CPU frequency" control API we can
migrate this code to using that.
Thanks to Michael Erikkson for providing this code!
is empty besides calling switch_exit(). So, rename switch_exit() to
cpu_exit() and modify the routine to call lwp_exit2() direct.
This saves couple cycles on the exit path.
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.
This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.
On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.
containing signal posting, kernel-exit handling and sa_upcall processing.
XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.
