u_int8_t array to struct ieee80211_nwid to prepend length field.
The length field is necessary because IEEE 802.11 spec doesn't prohibit
even '\0' for SSID.
Though the name and the value of SIOC... macro is unchanged, this change
breaks binary compatibility. The only affected userland program on the
tree is ifconfig(8).
As Jason suggested on tech-net, it is better than live with problems
since there are no releases for this ioctls yet.
arc4 implementation by Kalle Kaukonen has been added.
define "wlan" in files.
XXX: only awi depends on wlan for now.
Allow authentication for adhoc (IBSS) mode.
Disable adhoc mode without bssid (mediaopt adhoc,flag0) for FH radio.
FH cannot work without synchronization by beacons.
Align IP header for ethernet encapsulation (IFF_FLAG0) mode.
Print available access points for IFF_DEBUG.
- add amigappc devices
- add sgimips devices
- add cmpci, cy82c693, cz, fwbus, fwohci, sysmon, viaenv, viapm and xmi
- add necpb for arc
- add pcons for sparc64
- add xsii for pmax
- ncr for vax is renamed to si
- si for sparc is now MI
XXX siop for amigappc should be renamed to asiop?
apparently no longer necessary (probably due to other fixes that
have happened in the filter setup path) and is in fact harmful.
Based on a patch from Krister Walfridsson, who claims this makes
his newer NetGear FA-310TX work (although, my older NetGear FA-310TX
still does not, but fails in an entirely different way).
instead of discrete function pointers, and extend this to include
a "reset" entry point. Make sure any PHY-specific reset routine is
always used, and provide one for the LXT-970 which disables MII
interrupts (as is done for a few other PHYs we have drivers for).
which is revealed with larger HZ systems like NetBSD/pmax (256Hz)
and NetBSD/alpha (1024Hz) as reported by PR#8645. Polled tape
drive access is done with maximum 6 hour timeout which ended up
with negative time and then confused SCSI bus severely.
memory that is explicitly mapped in a DMA-coherent manner, we must
make sure to PREREAD sync the RFA after noticing a clear "complete"
bit. Without this, the clear bit will linger in the cache, and the
CPU will not notice when the chip updates the bit via DMA later.
From Izumi Tsutsui on port-arm32@netbsd.org.
nisimura