doshutdownhooks(9): shutdown hooks registered by shutdownhook_establish(9)
expect to be called with interrupts disabled, but shutdown hooks
registered with pmf_device_register1(9) expect to be called with
interrupts enabled. So I have made two changes:
1 Do not call pmf_system_shutdown() from doshutdownhooks(). Instead,
change every call to doshutdownhooks() to a call to doshutdownhooks()
followed by a call to pmf_system_shutdown(). No functional change
is intended by this change.
2 Make i386 re-enable interrupts briefly while it calls
pmf_system_shutdown(). I leave it to others either to fix the
other ports, or to factor out some MI shutdown code, as joerg@
suggests, and fix that. Note that a functional change *is* intended
by this change.
I hope that this patch will stop us from flip-flopping between
calling doshutdownhooks() and pmf_system_shutdown() sometimes with
and sometimes without interrupts enabled.
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:
Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
them in the mi "files" file, and remove include statements from md files.
These shouldn't pull in additional kernel code when not in use, so it
shouldn't do any harm except a risk of namespace collisions which
should be easy to fix.
the offset of a range. With this fix to the openpic initialization,
ofppc now boots single user on a 7046-B50. Thanks to Jochen Kunz for
giving me remote access to a B50 to hack on it.
on the 7043-150. The B50 wants not only a note at the head of the
binary, like the 7044 did, but it also wants a PHDR that points at it.
Because the IBM firmware doesn't like the real note section that ld
generates (it puts it at the end of the file), we instead point PT_NOTE
at the text section. This works, because at the top of the text section,
there is a note hacked in, which was required for the 7044.
Also, change the mode from virtual mode to real mode in the note, because
the B50 hangs if you load it in virtual. Tested to work on a B50, 7044,
and Pegasos2.
Yay IBM.
program that dumps the entire ofw device tree automatically. I needed
this functionality to collect ofw dumps from users, and it doesn't hurt
to just commit it, as it's all protected inside a #ifdef OFWDUMP.
PCI_NETBSD_CONFIGURE. Add some code to hopefully better handle the
firepower and powerstackII, based on the OFW dumps from those machines.
Untested on those machines, but doesn't break anything on pegasos/7044.
configuration of the machine is. Amusingly, the OFW on the pegasos is
dead wrong.
Bump CPU_MAXNUM to 8, because, thats probably a reasonable number for now.
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.
Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.
Yank __HAVE_PMAP_PHYSSEG from all the oea code.
Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.
Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.
In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].
With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.
Change the pegasos PCI_NETBSD_CONFIGURE arguments around to wire up mem
space into the correct area, and move the io regs a little to make it
work properly. Just avoid the secondary PCI entirely.
Change the list of things that we fiddle with in pci_conf_hook. Map mem
on the fwohci, avoid display cards, avoid IO on the auvia.
Change some printf's to aprint_*
Yank a call to genppc_pci_indirect_make_tag and change it to the
bus-independant pci call instead. (in pci_conf_hook)
where the bootloader would freak out if various printfs were enabled or
disabled.
Add code to autodetect a 64bit cpu, and attempt to load a different set
of kernels if they exist.
Bump version to 1.9
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.
Please note, this is a port of 32bit ofppc, not a powerpc64 port.
Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.
Summary of changes:
Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
the call to pci_configure_bus(9) and it's supporting code is
copied verbatim from the prep port.
this allows us to completely remove the really gross pegasos
specific pegasospci_indirect_attach_hook() that set various
pci command regs, since all those devices (mostly work now,
see below) and additionally PCI plugin cards work now too.
it also makes the pegasos onboard vr(4) ethernet work with
disk boot (it previously only worked with netboot.)
in the generic macppc ofw pci conf hook and for pegasos,
don't configure the viaide(4) device, and don't configure
memory space on the fwohci(4) device.
with this, and my other recent ofppc/ppc changes the pegasos
port is mostly functional. the marvell gige is not working,
and my 512mb appears as only about 256mb, but otherwise
this port is almost done!
global int machine_has_rtas that can be used to decide if a machine has
rtas functionality or not. Take a crack at power off support for the
pegasos, which doesn't work right, probably due to a firmware bug.
USB works fine. IEEE1394 is untested. Audio doesn't work (playing white noise).
Need to set IO/MEM-enable for IEEE1394 and audio, as the firmware (Smart
Firmware 1.2) doesn't do it.
Patch approved by Tim Rightnour.
once and for all. The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt). Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop. Non-i8259
handlers can safely ignore this argument.
Tested to fix the stream of 7's problem on prep and ofppc. Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.
ad