Commit Graph

13 Commits

Author SHA1 Message Date
scw a7be636d26 Rename the SH5 PCI attachment to "sh5pci" instead of abusing the "pcibus"
config definition. The new config world order is more picky about such things.
2002-09-28 13:08:22 +00:00
scw 251ba05b3f Support for the SH5 on-chip PCI bridge, and support for its deployment
in the Cayman board.
2002-09-28 11:16:36 +00:00
gehenna 77a6b82b27 Merge the gehenna-devsw branch into the trunk.
This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

	device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
  by using this grammer.

- Added the new naming convention.
  The name of the device switch must be <prefix>_[bc]devsw for auto-generation
  of device switch tables.

- The backward compatibility of loading block/character device
  switch by LKM framework is broken. This is necessary to convert
  from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
  We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
  the LKM framework will refer it to assign device major number dynamically.
2002-09-06 13:18:43 +00:00
scw 7da5ef1b84 Delete the CPU_CTB1 option; it was never used.
Add the SH5_INTC_IRL_MODE_INDEP option, to correctly configure
the interrupt controller for Cayman.
2002-08-30 11:25:09 +00:00
scw 877f6b7143 Add some options:
- SH5_SIM, as we're targetting the simulator.
 - KERNEL_IPT_SIZE, as we want to reduce startup time.
 - DDB. Yes, DDB inside a debugger/simulator. :)
2002-08-30 11:23:12 +00:00
scw 2ccf86d7da Re-sync with current reality.
Add options DDB.
Add debug makeoptions.
G/C some unnecessary stuff.
2002-08-26 11:16:02 +00:00
scw 9bcd736b9d Attach sm(4) at superio, instead of the previous isa bus attachment.
The latter's probe doesn't pick up the ethernet controller, and the
attach function needs to set MIIF_NOISOLATE.
We attach it at superio mainly because they share the same region of
address space, and the ethernet controller's interrupt is routed
through the superio.
2002-08-26 11:04:44 +00:00
scw d911ae5d57 SH5 systrace(5) glue. 2002-07-12 20:43:12 +00:00
scw e6115d56d5 Add some devices which should be present in the latest simulator. 2002-07-12 20:41:55 +00:00
scw 6daca7f652 Ditch the "simulated clock" hack. It would never really have worked,
and the latest simulator won't need it anyway.
2002-07-12 19:52:21 +00:00
scw e9688612da Make it so kernels can be compiled for 32-bit or 64-bit with a
simple config file option.

Also, don't hard code the endian setting in a header file. Rely instead
on the compiler defining __LITTLE_ENDIAN__ and DTRT as appropriate.
2002-07-12 19:33:27 +00:00
scw 0d0a6374ef Some cleanups for the MACHINE_ARCH endian suffix change. 2002-07-11 14:42:55 +00:00
scw 59474a8c82 NetBSD, meet the SH-5 cpu.
SH-5, meet NetBSD.

Let's hope this is the start of a long and fruitful relationship. :-)

This code, funded by Wasabi Systems, adds initial support for the
Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD.

At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator
which has no simulated devices other than a simple console. However, it
is good enough to get to the "root device: " prompt.

Device driver support for Real SH-5 Hardware is in place, particularly for
supporting the up-coming Cayman evaluation board, and should be quite
easy to get running when the hardware is available.

There is no in-tree toolchain for this port at this time. Gcc-current has
rudimentary SH-5 support but it is known to be buggy. A working toolchain
was obtained from SuperH to facilitate this port. Gcc-current will be
fixed in due course.

The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has
currently only been tested in 32-bit mode. It is bi-endian, via a boot-
time option and it also has an "SHcompact" mode in which it will execute
SH-[34] user-land instructions.

For more information on the SH-5, see www.superh.com. Suffice to say it
is *not* just another respin of the SH-[34].
2002-07-05 13:31:28 +00:00